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Verification of Processor Microarchitectures
San Diego, California April 26-April 30
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VTEST.1999.7666641999 17TH IEEE VLSI Test Symposium
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Jian Shen, Jacob A. Abraham, "Verification of Processor Microarchitectures," VLSI Test Symposium, IEEE, pp. 189, 1999 17TH IEEE VLSI Test Symposium, 1999.
 
 
BibTex
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@article{ 10.1109/VTEST.1999.766664,
author = {Jian Shen and Jacob A. Abraham},
title = {Verification of Processor Microarchitectures},
journal ={VLSI Test Symposium, IEEE},
volume = {0},
year = {1999},
issn = {1093-0167},
pages = {189},
doi = {http://doi.ieeecomputersociety.org/10.1109/VTEST.1999.766664},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
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TY - CONF
JO - VLSI Test Symposium, IEEE
TI - Verification of Processor Microarchitectures
SN - 1093-0167
SP
EP
A1 - Jian Shen,
A1 - Jacob A. Abraham,
PY - 1999
VL - 0
JA - VLSI Test Symposium, IEEE
ER -
 
Jian Shen, The University of Texas at Austin
Jacob A. Abraham, The University of Texas at Austin
This paper develops a new abstraction technique for processor microarchitecture validation. An abstract finite-state machine model is derived directly from the processor HDL description. This model, along with information about the instruction set, is used for validation coverage analysis. We also present automatic test generation algorithms for generating sequences for traversing state transition paths and covering snapshot and temporal events.
Citation:
Jian Shen, Jacob A. Abraham, "Verification of Processor Microarchitectures," vts, pp.189, 1999 17TH IEEE VLSI Test Symposium, 1999
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