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A Fault Simulation Based Test Pattern Generator for Synchronous Sequential Circuits
San Diego, California April 26-April 30
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VTEST.1999.7666741999 17TH IEEE VLSI Test Symposium
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Ruifeng Guo, Irith Pomeranz, Sudhakar M. Reddy, "A Fault Simulation Based Test Pattern Generator for Synchronous Sequential Circuits," VLSI Test Symposium, IEEE, pp. 260, 1999 17TH IEEE VLSI Test Symposium, 1999.
 
 
BibTex
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@article{ 10.1109/VTEST.1999.766674,
author = {Ruifeng Guo and Irith Pomeranz and Sudhakar M. Reddy},
title = {A Fault Simulation Based Test Pattern Generator for Synchronous Sequential Circuits},
journal ={VLSI Test Symposium, IEEE},
volume = {0},
year = {1999},
issn = {1093-0167},
pages = {260},
doi = {http://doi.ieeecomputersociety.org/10.1109/VTEST.1999.766674},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
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TY - CONF
JO - VLSI Test Symposium, IEEE
TI - A Fault Simulation Based Test Pattern Generator for Synchronous Sequential Circuits
SN - 1093-0167
SP
EP
A1 - Ruifeng Guo,
A1 - Irith Pomeranz,
A1 - Sudhakar M. Reddy,
PY - 1999
VL - 0
JA - VLSI Test Symposium, IEEE
ER -
 
Ruifeng Guo, University of Iowa
Irith Pomeranz, University of Iowa
Sudhakar M. Reddy, University of Iowa
We describe a fault simulation based test generation procedure for synchronous sequential circuits. Several techniques are used to generate test sequences to achieve high fault coverages at low computational complexity. Experimental results presented demonstrate that the proposed procedure achieves fault coverages which are in all cases the same or higher than those achieved by existing procedures. The run times of the procedure are considerably smaller compared to the existing procedures.
Citation:
Ruifeng Guo, Irith Pomeranz, Sudhakar M. Reddy, "A Fault Simulation Based Test Pattern Generator for Synchronous Sequential Circuits," vts, pp.260, 1999 17TH IEEE VLSI Test Symposium, 1999
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