Procedures for Identifying Undetectable and Redundant Faults In Synchronous Sequential Circuits

San Diego, California April 26-April 30

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http://doi.ieeecomputersociety.org/10.1109/VTEST.1999.766676

1999 17TH IEEE VLSI Test Symposium

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	Sudhakar M. Reddy, Irith Pomeranz, Nadir Z. Basturkmen, Xijiang Lin, "Procedures for Identifying Undetectable and Redundant Faults In Synchronous Sequential Circuits," VLSI Test Symposium, IEEE, pp. 275, 1999 17TH IEEE VLSI Test Symposium, 1999.

	BibTex	x
	@article{ 10.1109/VTEST.1999.766676, author = {Sudhakar M. Reddy and Irith Pomeranz and Nadir Z. Basturkmen and Xijiang Lin}, title = {Procedures for Identifying Undetectable and Redundant Faults In Synchronous Sequential Circuits}, journal ={VLSI Test Symposium, IEEE}, volume = {0}, year = {1999}, issn = {1093-0167}, pages = {275}, doi = {http://doi.ieeecomputersociety.org/10.1109/VTEST.1999.766676}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Test Symposium, IEEE TI - Procedures for Identifying Undetectable and Redundant Faults In Synchronous Sequential Circuits SN - 1093-0167 SP EP A1 - Sudhakar M. Reddy, A1 - Irith Pomeranz, A1 - Nadir Z. Basturkmen, A1 - Xijiang Lin, PY - 1999 VL - 0 JA - VLSI Test Symposium, IEEE ER -

Sudhakar M. Reddy, University of Iowa

Irith Pomeranz, University of Iowa

Nadir Z. Basturkmen, University of Iowa

Xijiang Lin, Mentor Graphics Corporation

We present three new procedures for identifying undetectable and redundant faults in synchronous sequential circuits. The cedures use an iterative logic array of limited length, into which faults are injected in different ways. The proposed procedures help identify undetectable and redundant faults that cannot be identified by existing procedures based on iterative logic arrays of limited length.

Citation:

Sudhakar M. Reddy, Irith Pomeranz, Nadir Z. Basturkmen, Xijiang Lin, "Procedures for Identifying Undetectable and Redundant Faults In Synchronous Sequential Circuits," vts, pp.275, 1999 17TH IEEE VLSI Test Symposium, 1999

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