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A Digital BIST for Operational Amplifiers Embedded in Mixed-Signal Circuits
San Diego, California April 26-April 30
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VTEST.1999.7666801999 17TH IEEE VLSI Test Symposium
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I. Rayane, TIMA / INPG
J. Velasco-Medina, TIMA / INPG
M. Nicolaidis, TIMA / INPG
A new digital BIST structure is proposed in this paper. During test mode, the Op Amp under test is placed in a voltage follower configuration in order to detect its slew-rate deviation, or in a comparator configuration in order to detect its signal propagation delay deviation. The test stimuli and the BIST control signals are simply derived from the test control signal TST using delay elements and logical gates. The test response is analyzed by using a pure digital circuitry. Simulation results show the effectiveness of the proposed technique with a low area overhead.
Citation:
I. Rayane, J. Velasco-Medina, M. Nicolaidis, "A Digital BIST for Operational Amplifiers Embedded in Mixed-Signal Circuits," vts, pp.304, 1999 17TH IEEE VLSI Test Symposium, 1999
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