Foreword

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Organizing Committee

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Steering Committee

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Program Committee

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Test Technology Technical Council

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Reviewers

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1998 Best Paper Award

pp. xxvii

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1998 Best Panel Award

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Overview of Tutorials

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VTS 1999 Keynote Address Embedded Test OR External Test

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Keynote Address

Vinod K. Agarwal, LogicVision, Inc.

pp. 2

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Design Technology Research and Education for Deep-Submicron Systems of the Next Century

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IEEE Xplore Subscribers

Invited Presentation

Hugo J. de Man, IMEC

pp. 8

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Testing High Speed VLSI Devices Using Slower Testers

Session 1: Testing High-Speed and Dynamic Circuits: Moderators: B. Courtois, TIMA

Angela Krstic

Kwang-Ting (Tim) Cheng

Srimat T. Chakradhar

pp. 16

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Built-in Test Pattern Generation For High-Performance Cir cuits Using Twisted-Ring Counters

Krishnendu Chakrabarty

Brian T. Murray

Vikram Iyengar

pp. 22

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The Limits of Digital Testing for Dynamic Circuits

R. Dean Adams, IBM

Edmond S. Cooley, Dartmouth College

pp. 28

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Instruction Randomization Self Test For Processor Cores

Session 2: Core Testing: Moderators: R. Garcia, Schlumberger

Ken Batcher, Case Western Reserve University

Christos Papachristou, Case Western Reserve University

pp. 34

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Testing of Non-Isolated Embedded Legacy Cores and their Surrounding Logic

Irith Pomeranz, University of Iowa

Yervant Zorian, LogicVision

pp. 41

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A New Totally Error Propagating Compactor for Arbitrary Cores with Digital Interfaces

M. Gössel, University of Potsdam

A. Morosov, University of Potsdam

E.S. Sogomonyan, Russian Academy of Science

pp. 49

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Multiple Design Error Diagnosis and Correction in Digital VLSI Circuits

Session 3: Diagnosis: Moderators: R. Galivanche, Intel

Andreas Veneris, University of Illinois at Urbana

Ibrahim N. Hajj, University of Illinois at Urbana

Srikanth Venkataraman, Intel Corporation

W. Kent Fuchs, Purdue University

pp. 58

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A New Method for Diagnosing Multiple Stuck-at Faults using Multiple and Single Fault Simulations

Hiroshi Takahashi, Ehime University

Kwame Osei Boateng, Ehime University

Yuzo Takamatsu, Ehime University

pp. 64

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Simulation-Based Design Error Diagnosis and Correction in Combinational Digital Circuits

Debashis Nayak

D.M.H. Walker

pp. 70

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Using Temporal Constraints for Eliminating Crosstalk Candidates for Design and Test

Session 4: Techniques for the Very-Deep Submicron: Moderators: L. Bouzaida, ST Microelectronics

Michael A. Margolese, University of California, at Santa Cruz

F. Joel Ferguson, University of California, at Santa Cruz

pp. 80

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Time Redundancy Based Soft-Error Tolerance to Rescue Nanometer Technologies

Michael Nicolaidis, TIMA

pp. 86

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Test Generation for Ground Bounce in Internal Logic Circuitry

Yi-Shing Chang, University of Southern California

Sandeep K. Gupta, University of Southern California

Melvin A. Breuer, University of Southern California

pp. 95

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Advanced Synchronous Scan Test Methodology for Multi Clock Domain ASICs

Session 5: Advanced Scan Path Techniques: Moderators: K. Ruparel, Cisco

Josef Schmid, Lucent Technologies

Joachim Knäblein, Lucent Technologies

pp. 106

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Scan Vector Compression/Decompression Using Statistical Coding

Abhijit Jas, University of Texas at Austin

Jayabrata Ghosh-Dastidar, University of Texas at Austin

Nur A. Touba, University of Texas at Austin

pp. 114

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Partial Scan Using Multi-Hop State Reachability Analysis

Sameer Sharma, Rutgers University

Michael S. Hsiao, Rutgers University

pp. 121

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Extending the Pseudo-Stuck-At Fault Model to Provide Complete IDDQ Coverage

Session 6: IDDQ Testing: Moderators: C. Hawkins, University of New Mexico

Robert C. Aitken, Hewlett-Packard Co.

pp. 128

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Built-In Current Sensor for IDDQ Testing in Deep Submicron CMOS

T. Calin, TIMA

L. Anghel, TIMA

M. Nicolaidis, TIMA

pp. 135

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On the Comparison of IDDQ and IDDQ Testing

C. Thibeault, ?cole de Technologie Sup?rieure

pp. 143

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A Flexible Path Selection Procedure for Path Delay Fault Testing

Session 7: Delay Fault Testing: Moderators: J. Aylor, University of Virginia

Irith Pomeranz, University of Iowa

Sudhakar M. Reddy, University of Iowa

pp. 152

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Delay Fault Testing of Designs with Embedded IP Cores

Hyungwon Kim, University of Michigan

John P. Hayes, University of Michigan

pp. 160

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Adaptive Techniques for Improving Delay Fault Diagnosis

Jayabrata Ghosh-Dastidar, University of Texas at Austin

Nur A. Touba, University of Texas at Austin

pp. 168

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On n-Detection Test Sets and Variable n-Detection Test Sets for Transition Faults

Irith Pomeranz, University of Iowa

Sudhakar M. Reddy, University of Iowa

pp. 173

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Validation Vector Grade (VVG): A New Coverage Metric for Validation and Test

Session 8: Validation, Verification, and Diagnosis: Moderators: D. Pradhan, Texas A&M University

Pradip A. Thaker

Vishwani D. Agrawal

Mona E. Zaghloul

pp. 182

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Verification of Processor Microarchitectures

Jian Shen, The University of Texas at Austin

Jacob A. Abraham, The University of Texas at Austin

pp. 189

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Techniques to Encode and Compress Fault Dictionaries

Sreejit Chakravarty, Intel Corporation

Vinodh Gopal, Compaq Computer Corp.

pp. 195

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Implication and Evaluation Techniques for Proving Fault Equivalence

M. Enamul Amyeen, Purdue University

W. Kent Fuchs, Purdue University

Irith Pomeranz, University of Iowa

Vamsi Boppana, Fujitsu Labs of America

pp. 201

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Efficient Test Generation for Transient Testing of Analog Circuits Using Partial Numerical Simulation

Session 9: Mixed Signal Testing: Moderators: G. Roberts, McGill University

Pramodchandran N. Variyam, Georgia Institute of Technology

Junwei Hou, Georgia Institute of Technology

Abhijit Chatterjee, Georgia Institute of Technology

pp. 214

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Specification Back-Propagation and Its Application to DC Fault Simulation for Analog/Mixed-Signal Circuits

Jiun-Lang Huang, University of California at Santa Barbara

Chen-Yang Pan, University of California at Santa Barbara

Kwang-Ting Cheng, University of California at Santa Barbara

pp. 220

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Test Metrics for Analog Parametric Faults

Stephen Sunter, LogicVision

Naveena Nagi, Advantest

pp. 226

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Comparative Study of CA-based PRPGs and LFSRs with Phase Shifters

Session 10: BIST: Moderators: S. Wu, Lucent Bell Labs

Janusz Rajski, Mentor Graphics Corporation

Grzegorz Mrugalski, Poznan University of Technology

Jerzy Tyszer, Poznan University of Technology

pp. 236

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An Efficient BIST Method for Small Buffers

W.B. Jone

D.C. Huang

S.C. Wu

K.J. Lee

pp. 246

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An Effective BIST Architecture for Sequential Fault Testing in Array Multipliers

Mihalis Psarakis, NCSR "Demokritos"

Antonis Paschalis, NCSR "Demokritos"

Dimitris Gizopoulos, 4PLUS Technologies

Yervant Zorian, LogicVision, Inc.

pp. 252

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A Fault Simulation Based Test Pattern Generator for Synchronous Sequential Circuits

Session 11: ATPG Related Approaches: Moderators: J. Sprock, Synopsys

Ruifeng Guo, University of Iowa

Irith Pomeranz, University of Iowa

Sudhakar M. Reddy, University of Iowa

pp. 260

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REDO - Probabilistic Excitation and Deterministic Observation - First Commercial Experiment

pp. 268

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Procedures for Identifying Undetectable and Redundant Faults In Synchronous Sequential Circuits

Sudhakar M. Reddy, University of Iowa

Irith Pomeranz, University of Iowa

Nadir Z. Basturkmen, University of Iowa

Xijiang Lin, Mentor Graphics Corporation

pp. 275

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A Novel Test Methodology for MEMS Magnetic Micromotors

Session 12: Testing MEMS, MCM and Analog Circuits: Moderators: D. Keezer, Georgia Tech

Bruce C. Kim, Michigan State University

Krishna Marella, Michigan State University

pp. 284

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A New Bare Die Test Methodology

Zao Yang, Silicon Graphics Inc.

K.-T. Cheng, University of California at Santa Barbara

K.L. Tai, Bell Laboratories

pp. 290

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Hierarchical Test Generation for Analog Circuits Using Incremental Test Development

Ramakrishna Voorakaranam, Georgia Institute of Technology

Abhijit Chatterjee, Georgia Institute of Technology

pp. 296

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A Digital BIST for Operational Amplifiers Embedded in Mixed-Signal Circuits

Session 13: Mixed Signal BIST: Moderators: B. Kaminska, Opmaxx

I. Rayane, TIMA / INPG

J. Velasco-Medina, TIMA / INPG

M. Nicolaidis, TIMA / INPG

pp. 304

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A Current Integrator for BIST of Mixed-Signal ICs

Sassan Tabatabaei, University of British Columbia

André Ivanov, University of British Columbia

pp. 311

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A Test Point Insertion Algorithm for Mixed-Signal Circuits

Jinyan Zhang, University of Washington

Sam Huynh, University of Washington

Mani Soma, University of Washington

pp. 319

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Defect-Oriented Verilog Fault Simulation of SoC Macros using a Stratified Fault Sampling Technique

Session 14: High-Level Test Techniques: Moderators: K. Kinoshita, Osaka University

pp. 326

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Behavioral Fault Modeling in a VHDL Synthesis Environment

Ronald J. Hayne, University of Virginia

Barry W. Johnson, University of Virginia

pp. 333

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RT-level TPG Exploiting High-Level Synthesis Information

Silvia Chiusano, Polit?cnico di Torino

Fulvio Corno, Polit?cnico di Torino

Paolo Prinetto, Polit?cnico di Torino

pp. 341

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Modular TSC Checkers for Bose-Lin and Bose Codes

Session 15: Concurrent Checking: Moderators: J. Huertas, Centro Nacional de Microelec

X. Kavousianos

D. Nikolos

pp. 354

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Programmable Embedded Self-Testing Checkers for All-Unidirectional Error-Detecting Codes

Albrecht P. Stroele, University of Karlsruhe

Steffen Tarnick, SATCON GmbH

pp. 361

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Weight-Based Codes and Their Application to Concurrent Error Detection of Multilevel Circuits

Debaleena Das

Nur A. Touba

pp. 370

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Maximal Diagnosis of Interconnects of Random Access Memories _

Session 16: Memory Test: Moderators: C.-W. Wu, Tsing Hua University

Jun Zhao, Texas A&M University

Fred J. Meyer, Northeastern University

Fabrizio Lombardi, Northeastern University

pp. 378

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Error Detecting Refreshment for Embedded DRAMs

pp. 384

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A New Framework For Automatic Generation, Insertion and Verification of Memory Built-In Self Test Units

Kamran Zarrineh

Shambhu J. Upadhyaya

pp. 391

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TAO-BIST: A Framework for Testability Analysis and Optimizationb of RTL Circuits for BIST

Session 17: BIST Related Approaches: Moderators: R. David, Lab d'Automatique de Grenoble

Srivaths Ravi

Ganesh Lakshminarayana

Niraj K. Jha

pp. 398

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A Test Vector Inhibiting Technique for Low Energy BIST Design

P. Girard, Universit? Montpellier

L. Guiller C. Landrault, Universit? Montpellier

S. Pravossoudovitch, Universit? Montpellier

pp. 407

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Enhanced Bist-Based Diagnosis of FPGAs via Boundary Scan Access

Carter Hamilton, University of Kentucky

Gretchen Gibson, University of Kentucky

Sajitha Wijesuriya, University of Kentucky

Charles Stroud, University of Kentucky

pp. 413

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Analyzing the Need for ATPG Targeting GOS Defects

Session 18: Defect Oriented Test: Moderators: Y. Malaiya, Colorado State University

E. Isern, Universit?t Illes Balears

M. Roca, Universit?t Illes Balears

J. Segura, Universit?t Illes Balears

pp. 420

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On the Evaluation of Arbitrary Defect Coverage of Test Sets

Ankur Jain, Rutgers University

Michael S. Hsiao, Rutgers University

Vamsi Boppana, Fujitsu Labs of America, Inc.

M. Fujita, Fujitsu Labs of America, Inc.

pp. 426

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Defect-Oriented Test Scheduling

Wanli Jiang, University of Minnesota

Bapiraju Vinnakota, University of Minnesota

pp. 433

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PADded Cache: A New Fault-Tolerance Technique for Cache Memories

Session 19: On-Line Testing and Fault Tolerance: Moderators: M. Bayoumi, University of Southwestern Louisiana

Philip P. Shirvani, Stanford University

Edward J. McCluskey, Stanford University

pp. 440

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Low-Cost On-Line Test for Digital Filters

Ismet Bayraktaroglu, University of California at San Diego

Alex Orailoglu, University of California at San Diego

pp. 446

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Evaluating the Fault Tolerance Capabilities of Embedded Systems via BDM

M. Rebaudengo, Polit?cnico di Torino

M. Sonza Reorda, Polit?cnico di Torino

pp. 452

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A Systematic DFT Procedure for Library Cells

Session 20: DFT and Boundary Scan: Moderators: S. Mourad, Santa Clara University

Jingjing Xu, University of California at Santa Cruz

Rahul Kundu, University of California at Santa Cruz

F. Joel Ferguson, University of California at Santa Cruz

pp. 460

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Instruction-Driven Wake-Up Mechanisms for Snoopy TAP Controller

Debashis Bhattacharya, Texas Instruments Incorporated

pp. 467

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From Design-for-Test to Design-for-Debug-and-Test: Analysis of Requirements and Limitations for 1149.1

Gustavo R. Alves, ISEP / DEE and FEUP / DEEC

J.M. Martins Ferreira, FEUP / DEEC

pp. 473

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Special Session 2: IEEE P1500: SOC Test Standardization: Moderator: K. Wagner, Stream Machine

P1500-CTL: Towards a Standard Core Test Language

Embedded Presentation: At-Speed Logic Built-In Self-Test: Moderator: J. Rajski, J. Tyszer

Author Index

pp. 487

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