A Framework to Minimize Test Escape and Yield Loss during IDDQ Testing: A Case Study

Montreal, Canada April 30-May 04

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http://doi.ieeecomputersociety.org/10.1109/VTEST.2000.843831

18th IEEE VLSI Test Symposium (VTS'00)

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	Hugo Cheung, Sandeep K. Gupta, "A Framework to Minimize Test Escape and Yield Loss during IDDQ Testing: A Case Study," VLSI Test Symposium, IEEE, pp. 89, 18th IEEE VLSI Test Symposium (VTS'00), 2000.

	BibTex	x
	@article{ 10.1109/VTEST.2000.843831, author = {Hugo Cheung and Sandeep K. Gupta}, title = {A Framework to Minimize Test Escape and Yield Loss during IDDQ Testing: A Case Study}, journal ={VLSI Test Symposium, IEEE}, volume = {0}, year = {2000}, issn = {1093-0167}, pages = {89}, doi = {http://doi.ieeecomputersociety.org/10.1109/VTEST.2000.843831}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Test Symposium, IEEE TI - A Framework to Minimize Test Escape and Yield Loss during IDDQ Testing: A Case Study SN - 1093-0167 SP EP A1 - Hugo Cheung, A1 - Sandeep K. Gupta, PY - 2000 KW - IDDQ KW - critical severity KW - test escape KW - yield loss KW - fault modeling VL - 0 JA - VLSI Test Symposium, IEEE ER -

Hugo Cheung, Burr-Brown Corporation

Sandeep K. Gupta, University of Southern California

We describe a new framework to minimize test escape (TE) and yield loss (YL) during IDDQ testing. The proposed framework defines the concept of critical severity of a fault Sk', that provides a link between the fault magnitude and violation of one or more specifications. The framework provides various strategies to select the values of IDDQ threshold and provides a mechanism to compute test escape and/or yield loss. The framework is illustrated using an SRAM as a case study. The results demonstrate various trade-off that can be explored using the framework.

Index Terms:

IDDQ, critical severity, test escape, yield loss, fault modeling

Citation:

Hugo Cheung, Sandeep K. Gupta, "A Framework to Minimize Test Escape and Yield Loss during IDDQ Testing: A Case Study," vts, pp.89, 18th IEEE VLSI Test Symposium (VTS'00), 2000

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