Integrating Logic BIST in VLSI Designs with Embedded Memories

Montreal, Canada April 30-May 04

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http://doi.ieeecomputersociety.org/10.1109/VTEST.2000.843840

18th IEEE VLSI Test Symposium (VTS'00)

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	Vivek Chickermane, Scott Richter, Carl Barnhart, "Integrating Logic BIST in VLSI Designs with Embedded Memories," VLSI Test Symposium, IEEE, pp. 157, 18th IEEE VLSI Test Symposium (VTS'00), 2000.

	BibTex	x
	@article{ 10.1109/VTEST.2000.843840, author = {Vivek Chickermane and Scott Richter and Carl Barnhart}, title = {Integrating Logic BIST in VLSI Designs with Embedded Memories}, journal ={VLSI Test Symposium, IEEE}, volume = {0}, year = {2000}, issn = {1093-0167}, pages = {157}, doi = {http://doi.ieeecomputersociety.org/10.1109/VTEST.2000.843840}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Test Symposium, IEEE TI - Integrating Logic BIST in VLSI Designs with Embedded Memories SN - 1093-0167 SP EP A1 - Vivek Chickermane, A1 - Scott Richter, A1 - Carl Barnhart, PY - 2000 VL - 0 JA - VLSI Test Symposium, IEEE ER -

Vivek Chickermane, IBM Corp.

Scott Richter, IBM Corp.

Carl Barnhart, IBM Corp.

Logic BIST techniques normally focus on testing random logic blocks. If one observes the current design trends for high-performance ASICS, the number and size of embedded memories is increasing rapidly. This presents several challenges to the design and integration of at-speed Logic BIST when the number of bits of embedded memories is a large percentage of the total number of storage bits in the design. This paper will discuss some novel techniques to address the DFT and clocking considerations in designs with extensive usage of embedded memories.

Citation:

Vivek Chickermane, Scott Richter, Carl Barnhart, "Integrating Logic BIST in VLSI Designs with Embedded Memories," vts, pp.157, 18th IEEE VLSI Test Symposium (VTS'00), 2000

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