Synthesis for Arithmetic Built-In Self-Test

Montreal, Canada April 30-May 04

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http://doi.ieeecomputersociety.org/10.1109/VTEST.2000.843841

18th IEEE VLSI Test Symposium (VTS'00)

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	Albrecht P. Stroele, "Synthesis for Arithmetic Built-In Self-Test," VLSI Test Symposium, IEEE, pp. 165, 18th IEEE VLSI Test Symposium (VTS'00), 2000.

	BibTex	x
	@article{ 10.1109/VTEST.2000.843841, author = {Albrecht P. Stroele}, title = {Synthesis for Arithmetic Built-In Self-Test}, journal ={VLSI Test Symposium, IEEE}, volume = {0}, year = {2000}, issn = {1093-0167}, pages = {165}, doi = {http://doi.ieeecomputersociety.org/10.1109/VTEST.2000.843841}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Test Symposium, IEEE TI - Synthesis for Arithmetic Built-In Self-Test SN - 1093-0167 SP EP A1 - Albrecht P. Stroele, PY - 2000 KW - Accumulator KW - built-in self-test KW - high-level synthesis KW - synthesis for testability KW - test configuration VL - 0 JA - VLSI Test Symposium, IEEE ER -

Albrecht P. Stroele, University of Karlsruhe

Arithmetic built-in self-test (BIST) is a favorable test method for data paths that include adders, subtracters, and other arithmetic units. With these functional units, accumulator structures are configured to generate test patterns and compact test responses.This paper presents a method to synthesize data paths that are well suited for arithmetic BIST. The key part of this approach is an assignment procedure that takes into account structural properties, which are advantageous for arithmetic BIST. The resulting circuits have the same speed and require about the same area as circuits that have been synthesized without testability considerations.

Index Terms:

Accumulator, built-in self-test, high-level synthesis, synthesis for testability, test configuration

Citation:

Albrecht P. Stroele, "Synthesis for Arithmetic Built-In Self-Test," vts, pp.165, 18th IEEE VLSI Test Symposium (VTS'00), 2000

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