An Effective Defect-Oriented BIST Architecture for High-Speed Phase-Locked Loops

Montreal, Canada April 30-May 04

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http://doi.ieeecomputersociety.org/10.1109/VTEST.2000.843850

18th IEEE VLSI Test Symposium (VTS'00)

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	Seongwon Kim, Mani Soma, Dilip Risbud, "An Effective Defect-Oriented BIST Architecture for High-Speed Phase-Locked Loops," VLSI Test Symposium, IEEE, pp. 231, 18th IEEE VLSI Test Symposium (VTS'00), 2000.

	BibTex	x
	@article{ 10.1109/VTEST.2000.843850, author = {Seongwon Kim and Mani Soma and Dilip Risbud}, title = {An Effective Defect-Oriented BIST Architecture for High-Speed Phase-Locked Loops}, journal ={VLSI Test Symposium, IEEE}, volume = {0}, year = {2000}, issn = {1093-0167}, pages = {231}, doi = {http://doi.ieeecomputersociety.org/10.1109/VTEST.2000.843850}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Test Symposium, IEEE TI - An Effective Defect-Oriented BIST Architecture for High-Speed Phase-Locked Loops SN - 1093-0167 SP EP A1 - Seongwon Kim, A1 - Mani Soma, A1 - Dilip Risbud, PY - 2000 KW - Built-In Self-Test (BIST) KW - Design for Testability KW - Self-Checking Circuits KW - Defect-oriented testing KW - PLL VL - 0 JA - VLSI Test Symposium, IEEE ER -

Seongwon Kim, University of Washington

Mani Soma, University of Washington

Dilip Risbud, National Semiconductor Corp.

We propose a new defect-oriented testing of PLL using charge-based frequency measurement BIST (CF-BIST) technique. As no test stimulus is required and the test output is pure digital, low-cost and practical implementation of on-chip BIST for a PLL is possible. Fault simulations using the 900MHz PLL from National Semiconductor Corp. show higher fault coverage than previous test methods.

Index Terms:

Built-In Self-Test (BIST), Design for Testability, Self-Checking Circuits, Defect-oriented testing, PLL

Citation:

Seongwon Kim, Mani Soma, Dilip Risbud, "An Effective Defect-Oriented BIST Architecture for High-Speed Phase-Locked Loops," vts, pp.231, 18th IEEE VLSI Test Symposium (VTS'00), 2000

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