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Detectability Conditions for Interconnection Open Defects
Montreal, Canada April 30-May 04
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VTEST.2000.84385918th IEEE VLSI Test Symposium (VTS'00)
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Victor H. Champac, Antonio Zenteno, "Detectability Conditions for Interconnection Open Defects," VLSI Test Symposium, IEEE, pp. 305, 18th IEEE VLSI Test Symposium (VTS'00), 2000.
 
 
BibTex
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@article{ 10.1109/VTEST.2000.843859,
author = {Victor H. Champac and Antonio Zenteno},
title = {Detectability Conditions for Interconnection Open Defects},
journal ={VLSI Test Symposium, IEEE},
volume = {0},
year = {2000},
issn = {1093-0167},
pages = {305},
doi = {http://doi.ieeecomputersociety.org/10.1109/VTEST.2000.843859},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
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TY - CONF
JO - VLSI Test Symposium, IEEE
TI - Detectability Conditions for Interconnection Open Defects
SN - 1093-0167
SP
EP
A1 - Victor H. Champac,
A1 - Antonio Zenteno,
PY - 2000
VL - 0
JA - VLSI Test Symposium, IEEE
ER -
 
Victor H. Champac, National Institute for Astrophysics, Optics and Electronics
Antonio Zenteno, National Institute for Astrophysics, Optics and Electronics
The detectability of interconnection opens by logic and IDDQ testing is investigated. Opens in interconnection paths disconnect the driven gate(s) from the driving gate. An electrical model for interconnection opens is used to predict the detectability of this type of opens. Using the proposed model, explicit analytical expressions have been obtained to determine the conditions for reliable detection of this defect by logic and IDDQ testing.The cases of full controllability and non-full controllability of the signals at the coupling lines have been analyzed. The effect of the trapped charge during fabrication has also been investigated. In addition, it has been found that the detectability of interconnection opens depends on the metal level where the signals are laid-out. The detectability dependency of interconnection opens on the test generation process has been analyzed.
Citation:
Victor H. Champac, Antonio Zenteno, "Detectability Conditions for Interconnection Open Defects," vts, pp.305, 18th IEEE VLSI Test Symposium (VTS'00), 2000
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