Foreword

HTML

IEEE Xplore Subscribers

Organizing Committee

pp. xv

PURCHASE ARTICLE: $0

HTML

IEEE Xplore Subscribers

Steering Committee

pp. xvii

PURCHASE ARTICLE: $0

HTML

IEEE Xplore Subscribers

Program Committee

pp. xix

PURCHASE ARTICLE: $0

HTML

IEEE Xplore Subscribers

Reviewers

pp. xxvii

PURCHASE ARTICLE: $0

HTML

IEEE Xplore Subscribers

VTS '99 Best Paper Award

pp. xxii

PURCHASE ARTICLE: $0

HTML

IEEE Xplore Subscribers

VTS '99 Best Panel Award

pp. xxiii

PURCHASE ARTICLE: $0

Test Technology Technical Council

HTML

IEEE Xplore Subscribers

pp. xxv

PURCHASE ARTICLE: $0

Test Technology Educational Program: Overview of Tutorials

HTML

IEEE Xplore Subscribers

pp. xxxi

PURCHASE ARTICLE: $0

Keynote Address: Optical Internet: Industry Challenges

HTML

IEEE Xplore Subscribers

Plenary Session

pp. xxxvii

PURCHASE ARTICLE: $0

At-Speed Testing of Delay Faults for Motorola's MPC7400, a PowerPC(tm) Microprocessor

HTML

IEEE Xplore Subscribers

Program Introduction

Invited Presentation: Wall Street Perspective on System-on-Chip and Test Technology

Session 1: Microprocessor Test/Validation

pp. 3

PDF

HTML

Validation of PowerPC(tm) Custom Memories using Symbolic Simulation

Narayanan Krishnamurthy, Motorola ASP Somerset Design Center

Andrew K. Martin, Motorola ASP Somerset Design Center

Magdy S. Abadir, Motorola ASP Somerset Design Center

Jacob A. Abraham, University of Texas at Austin

pp. 9

PDF

HTML

On Testing the Path Delay Faults of a Microprocessor Using its Instruction Set

Wei-Cheng Lai, University of California at Santa Barbara

Angela Krstic, University of California at Santa Barbara

Kwang-Ting (Tim) Cheng, University of California at Santa Barbara

pp. 15

PDF

HTML

Low Power/Energy BIST Scheme for Datapaths

Session 2: Low Power BIST and Scan

D. Gizopoulos, University of Piraeus

N. Kranitis, II&T, NCSR ?Demokritos?

M. Psarakis, II&T, NCSR ?Demokritos?

A Paschalis, University of Athens

Y. Zorian, LogicVision

pp. 23

PDF

HTML

Low Power BIST via Non-Linear Hybrid Cellular Automata

Fulvio Corno, Politecnico di Torino

Maurizio Rebaudengo, Politecnico di Torino

Matteo Sonza Reorda, Politecnico di Torino

Giovanni Squillero, Politecnico di Torino

Massimo Violante, Politecnico di Torino

pp. 29

PDF

HTML

Static Compaction Techniques to Control Scan Vector Power Dissipation

Ranganathan Sankaralingam, University of Texas at Austin

Rama Rao Oruganti, University of Texas at Austin

Nur A. Touba, University of Texas at Austin

pp. 35

PDF

HTML

Silicon-on-Insulator Technology Impacts on SRAM Testing

Session 3: Technology Trends and Their Impact on Test

R. Dean Adams, International Business Machines

Phil Shephard Iii, International Business Machines

pp. 43

PDF

HTML

Timing Analysis of Combinational Circuits Including Capacitive Coupling and Statistical Process Variation

Byungwoo Choi, Intel Corporation

D.M.H. Walker, Texas A&M University

pp. 49

PDF

HTML

Self-Checking Circuits versus Realistic Faults in Very Deep Submicron

Lorena Anghel, TIMA

Michael Nicolaidis, TIMA

Issam Alzaher-Noufal, TIMA

pp. 55

PDF

HTML

BSM2: Next Generation Boundary-Scan Master

Session 4: Scan Related Approaches

Frank P. Higgins, Bell Laboratories, Lucent Technologies

Rajagopalan Srinivasan, Bell Laboratories, Lucent Technologies

pp. 67

PDF

HTML

Virtual Scan Chains: A Means for Reducing Scan Length in Cores

Abhijit Jas, University of Texas at Austin

Bahram Pouya, University of Texas at Austin

Nur A. Touba, University of Texas at Austin

pp. 73

PDF

HTML

A Rapid and Scalable Diagnosis Scheme for BIST Environments with a Large Number of Scan Chains

Jayabrata Ghosh-Dastidar, University of Texas at Austin

Nur A. Touba, University of Texas at Austin

pp. 79

PDF

HTML

A Framework to Minimize Test Escape and Yield Loss during IDDQ Testing: A Case Study

Session 5: Defect Driven Techniques

Hugo Cheung, Burr-Brown Corporation

Sandeep K. Gupta, University of Southern California

pp. 89

PDF

HTML

Path Selection for Delay Testing of Deep Sub-Micron Devices Using Statistical Performance Sensitivity Analysis

Jing-Jia Liou, University of California at Santa Barbara

Kwang-Ting Cheng, University of California at Santa Barbara

Deb Aditya Mukherjee, Intel Corporation

pp. 97

PDF

HTML

PROBE: A PPSFP Simulator for Resistive Bridging Faults

Chul Young Lee, Compaq Computer Corporation

D.M.H. Walker, Texas A&M University

pp. 105

PDF

HTML

Test Data Compression for System-on-a-Chip Using Golomb Codes

Session 6: System-on-chip Test Techniques

Anshuman Chandra, Duke University

Krishnendu Chakrabarty, Duke University

pp. 113

PDF

HTML

Test and Debug of Networking SoCs: A Case Study

A. Bommireddy, Level One Communications

J. Khare, Level One Communications

S. Shaikh, Level One Communications

S-T. Su, Level One Communications

pp. 121

PDF

HTML

Design of System-on-a-Chip Test Access Architectures using Integer Linear Programming

Krishnendu Chakrabarty

pp. 127

PDF

HTML

Test Generation for Accurate Prediction of Analog Specifications

Session 7: Analog Test Techniques

Ram Voorakaranam, Georgia Institute of Technology

Abhijit Chatterjee, Georgia Institute of Technology

pp. 137

PDF

HTML

A Comprehensive TDM Comparator Scheme for Effective Analysis of Oscillation-Based Test

Jeongjin Roh, University of Texas at Austin

Jacob A. Abraham, University of Texas at Austin

pp. 143

PDF

HTML

Test Selection Based on High Level Fault Simulation for Mixed-Signal Systems

Sule Ozev, University of California at San Diego

Alex Orailoglu, University of California at San Diego

pp. 149

PDF

HTML

Integrating Logic BIST in VLSI Designs with Embedded Memories

Session 8: BIST: Arithmetic, Memories and ILAs

Vivek Chickermane, IBM Corp.

Scott Richter, IBM Corp.

Carl Barnhart, IBM Corp.

pp. 157

PDF

HTML

Synthesis for Arithmetic Built-In Self-Test

Albrecht P. Stroele, University of Karlsruhe

pp. 165

PDF

HTML

General BIST-Amenable Method of Test Generation for Iterative Logic Arrays

Kwame Osei Boateng, Ehime University

Hiroshi Takahashi, Ehime University

Yuzo Takamatsu, Ehime University

pp. 171

PDF

HTML

RF/Analog Test of Circuits and Systems

SPECIAL SESSION 2: Embedded Tutorial

M.S. Huetmaker, Lucent Technologies

pp. 179

PURCHASE ARTICLE: $0

Cold Delay Defect Screening

HTML

IEEE Xplore Subscribers

Session 9: Temperature and Process Drift Issues

Chao-Wen Tseng, Stanford University

Edward J. McCluskey, Stanford University

Xiaoping Shao, Intel Corporation

David M. Wu, Intel Corporation

pp. 183

PDF

HTML

Thermal Testing: Fault Location Strategies

J. Altet, Polytechnical University of Catalonia (UPC)

A. Rubio, Polytechnical University of Catalonia (UPC)

E. Schaub, Universite Bordeaux 1

S. Dialhaire, Universite Bordeaux 1

W. Claeys, Universite Bordeaux 1

pp. 189

PDF

HTML

Detection of CMOS Defects under Variable Processing Conditions

Amy Germida, University of Maryland at Baltimore County

James Plusquellic, University of Maryland at Baltimore County

pp. 195

PDF

HTML

SIFAR: Static Test Compaction for Synchronous Sequential Circuits Based on Single Fault Restoration

Session 10: Test Compaction and Design Validation

Xijiang Lin, Mentor Graphics Corporation

Wu-Tung Cheng, Mentor Graphics Corporation

Irith Pomeranz, University of Iowa

Sudhakar M. Reddy, University of Iowa

pp. 205

PDF

HTML

Space Compaction of Test Responses for IP Cores Using Orthogonal Transmission Functions

Markus Seuring

Krishnendu Chakrabarty

pp. 213

PDF

HTML

ESIM: A Multimodel Design Error and Fault Simulator for Logic Circuits

Hussain Al-Asaad, University of California at Davis

John P. Hayes, University of Michigan

pp. 221

PDF

HTML

An Effective Defect-Oriented BIST Architecture for High-Speed Phase-Locked Loops

Session 11: Analog BIST

Seongwon Kim, University of Washington

Mani Soma, University of Washington

Dilip Risbud, National Semiconductor Corp.

pp. 231

PDF

HTML

Characterization of a Pseudo-Random Testing Technique for Analog and Mixed-Signal Built-in-Self-Test

Jan Arild Tofte, Mentor Graphics Corporation

Chee-Kian Ong, University of California at Santa Barbara

Jiun-Lang Huang, University of California at Santa Barbara

Kwang-Ting (Tim) Cheng, University of California at Santa Barbara

pp. 237

PDF

HTML

Hardware Resource Minimization for Histogram-Based ADC BIST

M. Renovell, Universit? de Montpellier II

F. Azaïs, Universit? de Montpellier II

S. Bernard, Universit? de Montpellier II

Y. Bertrand, Universit? de Montpellier II

pp. 247

PDF

HTML

DEFUSE: A Deterministic Functional Self-Test Methodology for Processors

Session 12: Functional Test and Verification Issues

Li Chen, University of California at San Diego

Sujit Dey, University of California at San Diego

pp. 255

PDF

HTML

Testing, Verification, and Diagnosis in the Presence of Unknowns

A. Jain, Intel Corp.

V. Boppana, Fujitsu Labs. of America, Inc.

R. Mukherjee, Fujitsu Labs. of America, Inc.

J. Jain, Fujitsu Labs. of America, Inc.

M. ~Fujita, Fujitsu Labs. of America, Inc.

M. Hsiao, Rutgers University

pp. 263

PDF

HTML

Using Arithmetic Transform for Verification of Datapath Circuits via Error Modeling

Katarzyna Radecka, McGill University

Zeljko Zilic, McGill University

pp. 271

PDF

HTML

Functional Memory Faults: A Formal Notation and a Taxonomy

Session 13: Memory Test

Ad J. van de Goor, Delft University of Technology

Zaid Al-Ars, Delft University of Technology

pp. 281

PDF

HTML

Simulation-Based Test Algorithm Generation for Random Access Memories

Chi-Feng Wu, National Tsing Hua University

Chih-Tsun Huang, National Tsing Hua University

Kuo-Liang Cheng, National Tsing Hua University

Cheng-Wen Wu, National Tsing Hua University

pp. 291

PDF

HTML

Detection of Inter-Port Faults in Multi-Port Static RAMs

J. Zhao, Texas A&M University

S. Irrinki, LSI Logic Inc.

M. Puri, LSI Logic Inc.

F. Lombardi, Northeastern University

pp. 297

PDF

HTML

Detectability Conditions for Interconnection Open Defects

Session 14: Open Defect Detection, Diagnosis and Analog BIST

Victor H. Champac, National Institute for Astrophysics, Optics and Electronics

Antonio Zenteno, National Institute for Astrophysics, Optics and Electronics

pp. 305

PDF

HTML

A Technique for Logic Fault Diagnosis of Interconnect Open Defects

Srikanth Venkataraman, Intel Corporation

Scott B. Drummonds, Intel Corporation

pp. 313

PDF

HTML

Fault Detection Methodology and BIST Method for 2nd Order Butterworth, Chebyshev and Bessel Filter Approximations

José Vicente Calvano, Brazilian Navy Research Institute

Vladimir Castro Alves, Federal University. of Rio de Janeiro

Marcelo Lubaszewski, Federal University of Rio Grande do Sul

pp. 319

PDF

HTML

How Should Fault Coverage Be Defined?

SPECIAL SESSION 3: Open Projector

T.W. Williams, Synopsys

S. Sunter, Locic Vision

pp. 325

PURCHASE ARTICLE: $0

Biomedical ICs: What is Different about Testing those ICs?

HTML

IEEE Xplore Subscribers

SPECIAL SESSION 5: Panel

B. Vinnakota, University of Minnesota

Andre Ivanov, University of British Columbia

pp. 329

PURCHASE ARTICLE: $0

Bounding Circuit Delay by Testing a Very Small Subset of Paths

HTML

IEEE Xplore Subscribers

Session 15: Delay Test, Diagnosis and BIST

Manish Sharma, University of Illinois at Urbana-Champaign

Janak H. Patel, University of Illinois at Urbana-Champaign

pp. 333

PDF

HTML

On Test Set Generation for Efficient Path Delay Fault Diagnosis

Ramesh C. Tekumalla, Intel Corporation

pp. 343

PDF

HTML

A Low-Speed BIST Framework for High-Performance Circuit Testing

H.G. Kerkhoff, University of Twente

M. Shashaani, University of Waterloo

M. Sachdev, University of Waterloo

pp. 349

PDF

HTML

Hidden Markov and Independence Models with Patterns for Sequential BIST

Session 16: BIST Issues

Laurent Brehelin, Laboratoire d'Informatique, de Robotique et de Microelectronique de Montpellier

Olivier Gascuel, Laboratoire d'Informatique, de Robotique et de Microelectronique de Montpellier

Gilles Caraux, Laboratoire d'Informatique, de Robotique et de Microelectronique de Montpellier

Patrick Girard, Laboratoire d'Informatique, de Robotique et de Microelectronique de Montpellier

Christian Landrault, Laboratoire d'Informatique, de Robotique et de Microelectronique de Montpellier

pp. 359

PDF

HTML

Reducing Test Application Time for Built-in-Self-Test Test Pattern Generators

Ilker Hamzaoglu, University of Illinois at Urbana-Champaign

Janak H. Patel, University of Illinois at Urbana-Champaign

pp. 369

PDF

HTML

Linear Independence as Evaluation Criterion for Two-Dimensional Test Pattern Generators

Grzegorz Mrugalski, Poznan University of Technology

Jerzy Tyszer, Poznan University of Technology

Janusz Rajski, Mentor Graphics Corporation

pp. 377

PDF

HTML

P1450.1: STIL for the Simulation Environment

Session 17: STIL Extension, Jitter, and Crosstalk

Peter Wohl, Synopsys Inc.

Nathan Biggs, Priority Technologies Inc.

pp. 389

PDF

HTML

Extraction of Peak-to-Peak and RMS Sinusoidal Jitter Using an Analytic Signal Method

Takahiro J. Yamaguchi, Advantest Laboratories, Ltd.

Masahiro Ishida, Advantest Laboratories, Ltd.

Mani Soma, University of Washington

Toshifumi Watanabe, Advantest Corporation

Tadahiro Ohmi[4], Tohoku Universityapan

pp. 395

PDF

HTML

Crosstalk Effect Removal for Analog Measurement in Analog Test Bus

Chauchin Su, National Central University

Yue-Tsang Chen, National Central University

pp. 403

PDF

HTML

High-Level Observability for Effective High-Level ATPG

Session 18: High Level ATPG and Test Scheduling

Fulvio Corno, Politecnico di Torino

Matteo Sonza Reorda, Politecnico di Torino

Giovanni Squillero, Politecnico di Torino

pp. 411

PDF

HTML

The Left Edge Algorithm and the Tree Growing Technique in Block-Test Scheduling under Power Constraints

Valentin Muresan, Dublin City University

Xiaojun Wang, Dublin City University

Valentina Muresan, University of Timisoara

Mircea Vladutiu, University of Timisoara

pp. 417

PDF

HTML

Testability Alternatives Exploration through Functional Testing

F. Ferrandi, Politecnico di Milano

G. Fornara, Politecnico di Milano

D. Sciuto, Politecnico di Milano

G. Ferrara, Siemens Information and Communication Networks

F. Fummi, Universit? di Verona

pp. 423

PDF

HTML

Efficient Diagnosis of Single/Double Bridging Faults with Delta Iddq Probabilistic Signatures and Viterbi Algorithm

Session 19: IDDQ Test

C. Thibeault, ?cole de Technologie Sup?rieure

pp. 431

PDF

HTML

Delta Iddq for Testing Reliability

Theo J. Powell, Texas Instruments, Inc.

James Pair, Texas Instruments, Inc.

Melissa St. John, Texas Instruments, Inc.

Doug Counce, Texas Instruments, Inc.

pp. 439

PDF

HTML

Clustering Based Evaluation of IDDQ Measurements: Applications in Testing and Classification of ICs

Sri Jandhyala, Texas Instruments Inc.

Hari Balachandran, Texas Instruments Inc.

Manidip Sengupta, Texas Instruments Inc.

Anura P. Jayasumana, Colorado State University

pp. 444

PDF

HTML

Fault Escapes in Duplex Systems

Session 20: On-line Testing and Fault Tolerance

Subhasish Mitra, Stanford University

Nirmal R. Saxena, Stanford University

Edward J. McCluskey, Stanford University

pp. 453

PDF

HTML

Invariance-Based On-Line Test for RTL Controller-Datapath Circuits

Yiorgos Makris, University of California at San Diego

Ismet Bayraktaroglu, University of California at San Diego

Alex Orailoglu, University of California at San Diego

pp. 459

PDF

HTML

Word Voter: A New Voter Design for Triple Modular Redundant Systems

Subhasish Mitra, Stanford University

Edward J. McCluskey, Stanford University

pp. 465

PDF

HTML

Do I Need this Tool for My Chips to Work?

SPECIAL SESSION 7: Panel

F. Muradali, Agilent Technologies

A. Ivanov, University of British Columbia

pp. 471

PURCHASE ARTICLE: $0

High End and Low End Applications for Defective Chips: Enhanced Availability and Acceptability

HTML

IEEE Xplore Subscribers

SPECIAL SESSION 8: Panel

M. Breuer, USC

pp. 473

PURCHASE ARTICLE: $0

HTML

IEEE Xplore Subscribers

Author Index

pp. 475

PURCHASE ARTICLE: $0