loading...
On Diagnosing Path Delay Faults in an At-Speed Environment
Marina Del Rey, CA March 29-April 03
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VTS.2001.92341419th IEEE VLSI Test Symposium
 This Article 
 
PDF
HTML
 
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
Ramesh C. Tekumalla, Intel Corporation
Srikanth Venkataraman, Intel Corporation
Jayabrata Ghosh-Dastidar, University of Texas
Recent techniques for path delay fault diagnosis have addressed the problem in combinational circuits and sequential circuits. The root cause of a path delay fault test failure is narrowed down to a set of functionally sensitized paths and this set is further reduced by post processing the set of passing tests. In this paper, we present a method for narrowing down the suspects further to a set of segments on the failing functionally sensitized paths. The proposed method is implemented and applied to a set of industrial circuits and it is found to be very effective in determining the defective segments that explain excessive delays along paths.
Citation:
Ramesh C. Tekumalla, Srikanth Venkataraman, Jayabrata Ghosh-Dastidar, "On Diagnosing Path Delay Faults in an At-Speed Environment," vts, pp.0028, 19th IEEE VLSI Test Symposium, 2001
Usage of this product signifies your acceptance of the Terms of Use.