Scan Wheel - A Technique for Interfacing a High Speed Scan-Path with a Slow Speed Tester

Marina Del Rey, CA March 29-April 03

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http://doi.ieeecomputersociety.org/10.1109/VTS.2001.923424

19th IEEE VLSI Test Symposium

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	Dilip K. Bhavsar, "Scan Wheel - A Technique for Interfacing a High Speed Scan-Path with a Slow Speed Tester," VLSI Test Symposium, IEEE, pp. 0094, 19th IEEE VLSI Test Symposium, 2001.

	BibTex	x
	@article{ 10.1109/VTS.2001.923424, author = {Dilip K. Bhavsar}, title = {Scan Wheel - A Technique for Interfacing a High Speed Scan-Path with a Slow Speed Tester}, journal ={VLSI Test Symposium, IEEE}, volume = {0}, year = {2001}, isbn = {0-7695-1122-8}, pages = {0094}, doi = {http://doi.ieeecomputersociety.org/10.1109/VTS.2001.923424}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Test Symposium, IEEE TI - Scan Wheel - A Technique for Interfacing a High Speed Scan-Path with a Slow Speed Tester SN - 0-7695-1122-8 SP EP A1 - Dilip K. Bhavsar, PY - 2001 VL - 0 JA - VLSI Test Symposium, IEEE ER -

Dilip K. Bhavsar, Compaq Computer Corporation

A novel interface architecture allows slow-speed test equipment to control and access scan registers operating at the full clock rate of the chip or the system. The architecture requires simple on-chip hardware and works with a minimal number of chip pins.

Citation:

Dilip K. Bhavsar, "Scan Wheel - A Technique for Interfacing a High Speed Scan-Path with a Slow Speed Tester," vts, pp.0094, 19th IEEE VLSI Test Symposium, 2001

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