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Built-In-Chip Testing of Voltage Overshoots in High-Speed SoCs
Marina Del Rey, CA March 29-April 03
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VTS.2001.92342619th IEEE VLSI Test Symposium
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Amir Attarha, The University of Texas at Dallas
Mehrdad Nourani, The University of Tehran
We present a methodology to detect and measure the signal overshoots occurring on the interconnects of high-speed system-on-chips. Overshoots are known to inject hot-carriers into the gate oxide which cause permanent degradation of MOSFET transistors' performance over time. We propose a built-in chip mechanism to detect overshoots, collect the occurrence information and scan them out efficiently and inexpensively for built-in self-test, reliability analysis and diagnosis.
Citation:
Amir Attarha, Mehrdad Nourani, "Built-In-Chip Testing of Voltage Overshoots in High-Speed SoCs," vts, pp.0111, 19th IEEE VLSI Test Symposium, 2001
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