Socillator Test: A Delay Test Scheme for Embedded ICs in the Boundary-Scan Environment

Marina Del Rey, CA March 29-April 03

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http://doi.ieeecomputersociety.org/10.1109/VTS.2001.923433

19th IEEE VLSI Test Symposium

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	Tek Jau Tan, Chung Len Lee, "Socillator Test: A Delay Test Scheme for Embedded ICs in the Boundary-Scan Environment," VLSI Test Symposium, IEEE, pp. 0158, 19th IEEE VLSI Test Symposium, 2001.

	BibTex	x
	@article{ 10.1109/VTS.2001.923433, author = {Tek Jau Tan and Chung Len Lee}, title = {Socillator Test: A Delay Test Scheme for Embedded ICs in the Boundary-Scan Environment}, journal ={VLSI Test Symposium, IEEE}, volume = {0}, year = {2001}, isbn = {0-7695-1122-8}, pages = {0158}, doi = {http://doi.ieeecomputersociety.org/10.1109/VTS.2001.923433}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Test Symposium, IEEE TI - Socillator Test: A Delay Test Scheme for Embedded ICs in the Boundary-Scan Environment SN - 0-7695-1122-8 SP EP A1 - Tek Jau Tan, A1 - Chung Len Lee, PY - 2001 KW - Delay testing KW - Embedded testing KW - SOC testing KW - Oscillation test KW - System test. VL - 0 JA - VLSI Test Symposium, IEEE ER -

Tek Jau Tan, National Chiao Tung University

Chung Len Lee, National Chiao Tung University

A novel test scheme, which uses an oscillation source to supply the test signal and a transition detector to detect the arrival of the transition of the test signal through the CUT within the specific delay time, is proposed. The scheme is ideal to test embedded chips in the boundary scan environment within an SOC.

Index Terms:

Delay testing, Embedded testing, SOC testing, Oscillation test, System test.

Citation:

Tek Jau Tan, Chung Len Lee, "Socillator Test: A Delay Test Scheme for Embedded ICs in the Boundary-Scan Environment," vts, pp.0158, 19th IEEE VLSI Test Symposium, 2001

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