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RT-level Fault Simulation Based on Symbolic Propagation
Marina Del Rey, CA March 29-April 03
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VTS.2001.92344519th IEEE VLSI Test Symposium
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Ozgur Sinanoglu, Alex Orailoglu, "RT-level Fault Simulation Based on Symbolic Propagation," VLSI Test Symposium, IEEE, pp. 0240, 19th IEEE VLSI Test Symposium, 2001.
 
 
BibTex
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@article{ 10.1109/VTS.2001.923445,
author = {Ozgur Sinanoglu and Alex Orailoglu},
title = {RT-level Fault Simulation Based on Symbolic Propagation},
journal ={VLSI Test Symposium, IEEE},
volume = {0},
year = {2001},
isbn = {0-7695-1122-8},
pages = {0240},
doi = {http://doi.ieeecomputersociety.org/10.1109/VTS.2001.923445},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
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TY - CONF
JO - VLSI Test Symposium, IEEE
TI - RT-level Fault Simulation Based on Symbolic Propagation
SN - 0-7695-1122-8
SP
EP
A1 - Ozgur Sinanoglu,
A1 - Alex Orailoglu,
PY - 2001
VL - 0
JA - VLSI Test Symposium, IEEE
ER -
 
Ozgur Sinanoglu, University of California, San Diego
Alex Orailoglu, University of California, San Diego
The rapid rise in size and complexity of VLSI circuits has stimulated a need to handle fault simulation at higher levels of abstraction. We outline an RT-level fault simulation technique that utilizes symbolic data to group fault effects. Experimental results show that the proposed methodology provides superior speed-ups and accurate fault coverages.
Citation:
Ozgur Sinanoglu, Alex Orailoglu, "RT-level Fault Simulation Based on Symbolic Propagation," vts, pp.0240, 19th IEEE VLSI Test Symposium, 2001
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