A Low-Cost Adaptive Ramp Generator for Analog BIST Applications

Marina Del Rey, CA March 29-April 03

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http://doi.ieeecomputersociety.org/10.1109/VTS.2001.923449

19th IEEE VLSI Test Symposium

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	ASCII Text	x
	F. Azaïs, S. Bernard, Y. Bertrand, X. Michel, M. Renovell, "A Low-Cost Adaptive Ramp Generator for Analog BIST Applications," VLSI Test Symposium, IEEE, pp. 0266, 19th IEEE VLSI Test Symposium, 2001.

	BibTex	x
	@article{ 10.1109/VTS.2001.923449, author = {F. Azaïs and S. Bernard and Y. Bertrand and X. Michel and M. Renovell}, title = {A Low-Cost Adaptive Ramp Generator for Analog BIST Applications}, journal ={VLSI Test Symposium, IEEE}, volume = {0}, year = {2001}, isbn = {0-7695-1122-8}, pages = {0266}, doi = {http://doi.ieeecomputersociety.org/10.1109/VTS.2001.923449}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Test Symposium, IEEE TI - A Low-Cost Adaptive Ramp Generator for Analog BIST Applications SN - 0-7695-1122-8 SP EP A1 - F. Azaïs, A1 - S. Bernard, A1 - Y. Bertrand, A1 - X. Michel, A1 - M. Renovell, PY - 2001 VL - 0 JA - VLSI Test Symposium, IEEE ER -

F. Azaïs, University of Montpellier

S. Bernard, University of Montpellier

Y. Bertrand, University of Montpellier

X. Michel, University of Montpellier

M. Renovell, University of Montpellier

This paper presents a high-quality and area-efficient ramp generator to be used for on-chip testing of analog and mixed-signal circuits. An original adaptive scheme is developed to palliate the inaccuracy of a basic ramp generator. As a result, the proposed adaptive ramp generator exhibits very good performances in terms of slope precision and ramp linearity while maintaining a low area overhead.

Citation:

F. Azaïs, S. Bernard, Y. Bertrand, X. Michel, M. Renovell, "A Low-Cost Adaptive Ramp Generator for Analog BIST Applications," vts, pp.0266, 19th IEEE VLSI Test Symposium, 2001

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