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Defect Oriented Fault Diagnosis for Semiconductor Memories using Charge Analysis: Theory and Experiments
Marina Del Rey, CA March 29-April 03
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VTS.2001.92345119th IEEE VLSI Test Symposium
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I. de Paúl, University Illes Balears
M. Rosales, University Illes Balears
B. Alorda, University Illes Balears
J. Segura, University Illes Balears
C. Hawkins, The University of New Mexico
J. Soden, Sandia National Labs
We evaluated a diagnostic technique based on the charge delivered to the IC during a transition. Charge computed from the transient supply current is related to the circuit internal activity. A specific activity can be forced into the circuit using appropriate test vectors to highlight possible defect locations. Experimental results from a small test circuit and a 256K SRAM demonstrate the experimental viability of the technique. The theoretical foundation is also discussed.
Citation:
I. de Paúl, M. Rosales, B. Alorda, J. Segura, C. Hawkins, J. Soden, "Defect Oriented Fault Diagnosis for Semiconductor Memories using Charge Analysis: Theory and Experiments," vts, pp.0286, 19th IEEE VLSI Test Symposium, 2001
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