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Scan Islands - A Scan Partitioning Architecture and its Implementation on the Alpha 21364 Processor
Monterey, California April 28-May 02
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VTS.2002.101110520th IEEE VLSI Test Symposium
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Dilip K. Bhavsar, Richard A. Davies, "Scan Islands - A Scan Partitioning Architecture and its Implementation on the Alpha 21364 Processor," VLSI Test Symposium, IEEE, pp. 0016, 20th IEEE VLSI Test Symposium, 2002.
 
 
BibTex
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@article{ 10.1109/VTS.2002.1011105,
author = {Dilip K. Bhavsar and Richard A. Davies},
title = {Scan Islands - A Scan Partitioning Architecture and its Implementation on the Alpha 21364 Processor},
journal ={VLSI Test Symposium, IEEE},
volume = {0},
year = {2002},
isbn = {0-7695-1570-3},
pages = {0016},
doi = {http://doi.ieeecomputersociety.org/10.1109/VTS.2002.1011105},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - VLSI Test Symposium, IEEE
TI - Scan Islands - A Scan Partitioning Architecture and its Implementation on the Alpha 21364 Processor
SN - 0-7695-1570-3
SP
EP
A1 - Dilip K. Bhavsar,
A1 - Richard A. Davies,
PY - 2002
VL - 0
JA - VLSI Test Symposium, IEEE
ER -
 
Dilip K. Bhavsar, Intel Corporation
Richard A. Davies, Compaq Computer Corporation
The paper presents a pragmatic scan partitioning architecture that allows less than perfect scan design in high performance, VLSI circuits to cost-effectively achieve test development and manufacturing test goals. The paper then describes an implementation of the architecture on Compaq's Alpha 21364 microprocessor.
Citation:
Dilip K. Bhavsar, Richard A. Davies, "Scan Islands - A Scan Partitioning Architecture and its Implementation on the Alpha 21364 Processor," vts, pp.0016, 20th IEEE VLSI Test Symposium, 2002
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