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Spectrum-Based BIST in Complex SOCs
Monterey, California April 28-May 02
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VTS.2002.101112020th IEEE VLSI Test Symposium
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Ganapathy Kasturirangan, Intel Corporation
Michael S. Hsiao, Virginia Tech
We present a spectral built-in-self-test (BIST) for a system-on-a-chip (SOC) environment. Test vectors are generated using the spectral properties of the embedded cores. Because some embedded cores may not have direct connections to the embedded TPG, it would be necessary to test them via other cores. As a result, testing such (cascaded) cores requires considerations on the spectral characteristics of the predecessor and successor cores. Matching spectral characteristics between the outputs of the predecessor core and dominant inputs of the successor core allows the successor core to be more testable. Experimental results for the spectral BIST showed that significantly more faults can be detected using spectral patterns than by conventional weighted random BIST technique.
Citation:
Ganapathy Kasturirangan, Michael S. Hsiao, "Spectrum-Based BIST in Complex SOCs," vts, pp.0111, 20th IEEE VLSI Test Symposium, 2002
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