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A Self Calibrated ADC BIST Methodology
Monterey, California April 28-May 02
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VTS.2002.101112120th IEEE VLSI Test Symposium
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Hung-kai Chen, Chih-hu Wang, Chau-chin Su, "A Self Calibrated ADC BIST Methodology," VLSI Test Symposium, IEEE, pp. 0117, 20th IEEE VLSI Test Symposium, 2002.
 
 
BibTex
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@article{ 10.1109/VTS.2002.1011121,
author = {Hung-kai Chen and Chih-hu Wang and Chau-chin Su},
title = {A Self Calibrated ADC BIST Methodology},
journal ={VLSI Test Symposium, IEEE},
volume = {0},
year = {2002},
isbn = {0-7695-1570-3},
pages = {0117},
doi = {http://doi.ieeecomputersociety.org/10.1109/VTS.2002.1011121},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
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TY - CONF
JO - VLSI Test Symposium, IEEE
TI - A Self Calibrated ADC BIST Methodology
SN - 0-7695-1570-3
SP
EP
A1 - Hung-kai Chen,
A1 - Chih-hu Wang,
A1 - Chau-chin Su,
PY - 2002
VL - 0
JA - VLSI Test Symposium, IEEE
ER -
 
Hung-kai Chen, Nation Central University
Chih-hu Wang, Nation Central University
Chau-chin Su, Nation Central University
A self calibrated BIST methodology is proposed to overcome the process variation of the BIST circuitry. Two test methods are proposed, one by statistical analysis and another by curve fitting. Test hardware is built by discrete components to emulate the ADC BIST circuitry. Experimental results verify the feasibility of the methodology.
Citation:
Hung-kai Chen, Chih-hu Wang, Chau-chin Su, "A Self Calibrated ADC BIST Methodology," vts, pp.0117, 20th IEEE VLSI Test Symposium, 2002
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