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A Reconfigurable Shared Scan-in Architecture
Napa Valley, California April 27-May 01
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VTEST.2003.119762721st IEEE VLSI Test Symposium
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Samitha Samaranayake, Emil Gizdarski, Nodari Sitchinava, Frederic Neuveux, Rohit Kapur, T. W. Williams, "A Reconfigurable Shared Scan-in Architecture," VLSI Test Symposium, IEEE, pp. 9, 21st IEEE VLSI Test Symposium, 2003.
 
 
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@article{ 10.1109/VTEST.2003.1197627,
author = {Samitha Samaranayake and Emil Gizdarski and Nodari Sitchinava and Frederic Neuveux and Rohit Kapur and T. W. Williams},
title = {A Reconfigurable Shared Scan-in Architecture},
journal ={VLSI Test Symposium, IEEE},
volume = {0},
year = {2003},
issn = {1093-0167},
pages = {9},
doi = {http://doi.ieeecomputersociety.org/10.1109/VTEST.2003.1197627},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
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TY - CONF
JO - VLSI Test Symposium, IEEE
TI - A Reconfigurable Shared Scan-in Architecture
SN - 1093-0167
SP
EP
A1 - Samitha Samaranayake,
A1 - Emil Gizdarski,
A1 - Nodari Sitchinava,
A1 - Frederic Neuveux,
A1 - Rohit Kapur,
A1 - T. W. Williams,
PY - 2003
KW - null
VL - 0
JA - VLSI Test Symposium, IEEE
ER -
 
Samitha Samaranayake, Massachusetts Institute of Technology
Emil Gizdarski, Synopsys Inc.
Nodari Sitchinava, Massachusetts Institute of Technology
Frederic Neuveux, Synopsys Inc.
Rohit Kapur, Synopsys Inc.
T. W. Williams, Synopsys Inc.
In this paper, an efficient technique for test data volume reduction based on the shared scan-in (Illinois Scan) architecture and the scan chain reconfiguration (Dynamic Scan) architecture is defined. The composite architecture is created with analysis that relies on the compatibility relation of scan chains. Topological analysis and compatibility analysis are used to maximize gains in test data volume and test application time. The goal of the proposed synthesis procedure is to test all detectable faults in broadcast test mode using minimum scan-chain configurations. As a result, more aggressive sharing of scan inputs can be applied for test data volume and test application time reduction. The experimental results demonstrate the efficiency of the proposed architecture for real-industrial circuits.
Citation:
Samitha Samaranayake, Emil Gizdarski, Nodari Sitchinava, Frederic Neuveux, Rohit Kapur, T. W. Williams, "A Reconfigurable Shared Scan-in Architecture," vts, pp.9, 21st IEEE VLSI Test Symposium, 2003
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