A reduced intrinsic threshold voltage (V_T) in addition to its variability has a direct impact on circuit design. Worst-case design styles assume that all transistors use the same worst-case V_T whose average and standard deviation come from inter-die statistical variations. However, intra-die differences, such as random local V_T variations are not considered and may pose a serious problem for designs based on low-voltage low-power premises, e.g. clock skews, excessive leakage current, out of spec critical-path delays, etc. This paper formulates a fault model based on threshold voltage mismatch and analyzes its impact on circuit design. Simulation and experimental results support the fault model.