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Efficient Seed Utilization for Reseeding based Compression
Napa Valley, California April 27-May 01
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VTEST.2003.119765621st IEEE VLSI Test Symposium
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Erik H. Volkerink, Stanford University; Agilent Laboratories
Subhasish Mitra, Intel Corporation
The conventional LFSR reseeding technique for test data compression generates one test pattern from each LFSR seed. The seed size is determined by the maximum number of specified bits in a test pattern belonging to a given test set. However, for most practical designs the majority of test patterns have significantly fewer specified bits compared to the maximum. This limits the amount of compression that can be achieved with conventional reseeding. This paper presents a new reseeding technique that overcomes this problem by generating a single test pattern from multiple seeds and multiple test patterns from a single seed. The new reseeding technique is applied to two industrial designs resulting in significant reduction in tester memory requirement and test application time compared to the conventional reseeding technique.
Citation:
Erik H. Volkerink, Subhasish Mitra, "Efficient Seed Utilization for Reseeding based Compression," vts, pp.232, 21st IEEE VLSI Test Symposium, 2003
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