This paper improves upon the state of the art in testing word oriented memories. It first presents a complete set of fault models for intra-word couplinmg faults. Then, it establishes the data background sequence (DBS) for each intra-word coupling fault. These DBSs will be compiled into a (1 + 28 \times [log2B]) \times {n\over B} test with complete fault coverage of the target faults, where n is the size of the memory and B the word size. The test length can be reduced to 29 \times {n\over B} when the intra-word faults are restricted to physical adjacent cells within a word.
Index Terms:
Bit-oriented/word-oriented memories, memory tests, data backgrounds, fault models
Citation:
Said Hamdioui, Ad J. van de Goor, Mike Rodgers, "Detecting Intra-Word Faults in Word-Oriented Memories," vts, pp.241, 21st IEEE VLSI Test Symposium, 2003