loading...
Test and Diagnosis of Word-Oriented Multiport Memories
Napa Valley, California April 27-May 01
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VTEST.2003.119765821st IEEE VLSI Test Symposium
 This Article 
 
PDF
HTML
 
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
Chih-Wea Wang, National Tsing Hua University
Kuo-Liang Cheng, National Tsing Hua University
Chih-Tsun Huang, National Tsing Hua University
Cheng-Wen Wu, National Tsing Hua University
Conventionally, the test of multiport memories is considered difficult because of the complex behavior of the faulty memories and the large number of inter-port faults. This paper presents an efficient approach for testing and diagnosing multiport RAMs. Our approach takes advantage of the higher access bandwidth due to the increased number of read/write ports, which also provides higher observability and controllability that effectively reduces the test time. Our key idea is that a sequence of March operations for any memory cell can be folded and executed within a single access cycle. We have also developed an efficient test algorithm for port-specific faults as well as traditional cell faults. The port-specific faults include the stuck-open, address decoder, and inter-port faults, for both bit-oriented and word-oriented RAMs. Experimental results for our folding scheme show that the test time reduction is about 28% for a commercial 8 KB embedded SRAM. An efficient diagnostic algorithm is also proposed for the port-specific faults and traditional cell faults.
Citation:
Chih-Wea Wang, Kuo-Liang Cheng, Chih-Tsun Huang, Cheng-Wen Wu, "Test and Diagnosis of Word-Oriented Multiport Memories," vts, pp.248, 21st IEEE VLSI Test Symposium, 2003
Usage of this product signifies your acceptance of the Terms of Use.