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Test Resource Partitioning and Optimization for SOC Designs
Napa Valley, California April 27-May 01
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VTEST.2003.119766921st IEEE VLSI Test Symposium
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Erik Larsson, Hideo Fujiwara, "Test Resource Partitioning and Optimization for SOC Designs," VLSI Test Symposium, IEEE, pp. 319, 21st IEEE VLSI Test Symposium, 2003.
 
 
BibTex
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@article{ 10.1109/VTEST.2003.1197669,
author = {Erik Larsson and Hideo Fujiwara},
title = {Test Resource Partitioning and Optimization for SOC Designs},
journal ={VLSI Test Symposium, IEEE},
volume = {0},
year = {2003},
issn = {1093-0167},
pages = {319},
doi = {http://doi.ieeecomputersociety.org/10.1109/VTEST.2003.1197669},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
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TY - CONF
JO - VLSI Test Symposium, IEEE
TI - Test Resource Partitioning and Optimization for SOC Designs
SN - 1093-0167
SP
EP
A1 - Erik Larsson,
A1 - Hideo Fujiwara,
PY - 2003
KW - null
VL - 0
JA - VLSI Test Symposium, IEEE
ER -
 
Erik Larsson, Linkopings Universitet; Nara Institute of Science and Technology
Hideo Fujiwara, Nara Institute of Science and Technology
We propose a test resource partitioning and optimization technique for core-based designs. Our technique includes test set selection and test resource floor-planning with the aim of minimizing the total test application time and the routing of the added TAM (test access mechanism) wires. A feature of our approach is that it pinpoints bottlenecks that are likely to limit the test solution, which is important in the iterative test solution development process. We demonstrate the usefulness of the technique through a comparison with a test scheduling and TAM design tool.
Citation:
Erik Larsson, Hideo Fujiwara, "Test Resource Partitioning and Optimization for SOC Designs," vts, pp.319, 21st IEEE VLSI Test Symposium, 2003
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