loading...
Built-in Current Sensor for ∆I{DDQ} Testing of Deep Submicron Digital CMOS ICs
Napa Valley, California April 25-April 29
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VTEST.2004.129922522nd IEEE VLSI Test Symposium
 This Article 
 
Buy PURCHASE ARTICLE: $19
PDF
HTML
Buy IEEE Xplore Subscribers
 
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
ASCII Text
x 
 
Josep Rius V?zquez, Jos? Pineda de Gyvez, "Built-in Current Sensor for ∆I{DDQ} Testing of Deep Submicron Digital CMOS ICs," VLSI Test Symposium, IEEE, pp. 53, 22nd IEEE VLSI Test Symposium, 2004.
 
 
BibTex
x
 
@article{ 10.1109/VTEST.2004.1299225,
author = {Josep Rius V?zquez and Jos? Pineda de Gyvez},
title = {Built-in Current Sensor for ∆I{DDQ} Testing of Deep Submicron Digital CMOS ICs},
journal ={VLSI Test Symposium, IEEE},
volume = {0},
year = {2004},
issn = {1093-0167},
pages = {53},
doi = {http://doi.ieeecomputersociety.org/10.1109/VTEST.2004.1299225},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - VLSI Test Symposium, IEEE
TI - Built-in Current Sensor for ∆I{DDQ} Testing of Deep Submicron Digital CMOS ICs
SN - 1093-0167
SP
EP
A1 - Josep Rius V?zquez,
A1 - Jos? Pineda de Gyvez,
PY - 2004
KW - null
VL - 0
JA - VLSI Test Symposium, IEEE
ER -
 
Josep Rius V?zquez, Universitat Polit?cnica de Catalunya, Spain
Jos? Pineda de Gyvez, Philips Research Laboratories, The Netherlands
This paper presents the implementation of a built-in current sensor that includes two recently reported new techniques for I{DDQ} testing to take into account the increased background current of defect-free circuits and its increased variance due to process variations. These techniques are the correlation between speed and I{DDQ}, and the ∆I{DDQ} testing technique. The monitor has been manufactured in a 0.18 ?m CMOS technology and it is based on the principle of disconnecting the device under test from the power supply during the testing phase. The monitor has a resolution of 1 ?A for a background current less than 100 ?A or 1% of background currents over 100 ?A to a total of 1mA full-scale. The sensor operates at a maximum clock speed of 250MHz. The monitor has been verified in a test chip consisting of one "DSP like" circuit of about 250,000 transistors. Experimental results prove the usefulness of our approach as a quick and effective means for detecting defects.
Citation:
Josep Rius V?zquez, Jos? Pineda de Gyvez, "Built-in Current Sensor for ∆I{DDQ} Testing of Deep Submicron Digital CMOS ICs," vts, pp.53, 22nd IEEE VLSI Test Symposium, 2004
Usage of this product signifies your acceptance of the Terms of Use.