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On Comparison of NCR Effectiveness with a Reduced I{DDQ} Vector Set
Napa Valley, California April 25-April 29
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VTEST.2004.129922722nd IEEE VLSI Test Symposium
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Sagar Sabade, D. M. H. Walker, "On Comparison of NCR Effectiveness with a Reduced I{DDQ} Vector Set," VLSI Test Symposium, IEEE, pp. 65, 22nd IEEE VLSI Test Symposium, 2004.
 
 
BibTex
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@article{ 10.1109/VTEST.2004.1299227,
author = {Sagar Sabade and D. M. H. Walker},
title = {On Comparison of NCR Effectiveness with a Reduced I{DDQ} Vector Set},
journal ={VLSI Test Symposium, IEEE},
volume = {0},
year = {2004},
issn = {1093-0167},
pages = {65},
doi = {http://doi.ieeecomputersociety.org/10.1109/VTEST.2004.1299227},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
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TY - CONF
JO - VLSI Test Symposium, IEEE
TI - On Comparison of NCR Effectiveness with a Reduced I{DDQ} Vector Set
SN - 1093-0167
SP
EP
A1 - Sagar Sabade,
A1 - D. M. H. Walker,
PY - 2004
KW - null
VL - 0
JA - VLSI Test Symposium, IEEE
ER -
 
Sagar Sabade, Texas A&M University, College Station
D. M. H. Walker, Texas A&M University, College Station
I{DDQ} test-based outlier rejection becomes difficult for deep sub-micron technology chips due to increased leakage and process variations. The use of Neighbor Current Ratio (NCR) that uses wafer-level spatial correlation for identifying outlier chips has been proposed earlier as a means of coping with these issues. Due to the slow speed of I{DDQ} test, there is a strong motivation to reduce the number of test vectors without compromising the fault coverage. In this paper, we examine the effectiveness of Neighbor Current Ratio using a reduced I{DDQ} vector set and industrial test data.
Citation:
Sagar Sabade, D. M. H. Walker, "On Comparison of NCR Effectiveness with a Reduced I{DDQ} Vector Set," vts, pp.65, 22nd IEEE VLSI Test Symposium, 2004
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