loading...
FPGA Bridging Fault Detection and Location via Differential I{DDQ}
Napa Valley, California April 25-April 29
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VTEST.2004.129923322nd IEEE VLSI Test Symposium
 This Article 
 
Buy PURCHASE ARTICLE: $19
PDF
HTML
IEEE Xplore Subscribers
 
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
ASCII Text
x 
 
Erik Chmelar, Shahin Toutounchi, "FPGA Bridging Fault Detection and Location via Differential I{DDQ}," VLSI Test Symposium, IEEE, pp. 109, 22nd IEEE VLSI Test Symposium, 2004.
 
 
BibTex
x
 
@article{ 10.1109/VTEST.2004.1299233,
author = {Erik Chmelar and Shahin Toutounchi},
title = {FPGA Bridging Fault Detection and Location via Differential I{DDQ}},
journal ={VLSI Test Symposium, IEEE},
volume = {0},
year = {2004},
issn = {1093-0167},
pages = {109},
doi = {http://doi.ieeecomputersociety.org/10.1109/VTEST.2004.1299233},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - VLSI Test Symposium, IEEE
TI - FPGA Bridging Fault Detection and Location via Differential I{DDQ}
SN - 1093-0167
SP
EP
A1 - Erik Chmelar,
A1 - Shahin Toutounchi,
PY - 2004
KW - null
VL - 0
JA - VLSI Test Symposium, IEEE
ER -
 
Erik Chmelar, Stanford University
Shahin Toutounchi, Xilinx, Inc.
Standard I{DDQ} testing is limited by the ability to distinguish a small fault current from a large background leakage current: this limitation is overcome in FPGAs by differential I{DDQ} testing. Partitioning of interconnects further increases the detectability of a fault current.
Fault location can be achieved by iteratively applying partitioned differential I{DDQ} testing to eliminate fault-free nets. The location algorithm, easily automated, requires very few configurations and I{DDQ} measurements, logarithmic to the number of initially-suspected faulty nets.
Citation:
Erik Chmelar, Shahin Toutounchi, "FPGA Bridging Fault Detection and Location via Differential I{DDQ}," vts, pp.109, 22nd IEEE VLSI Test Symposium, 2004
Usage of this product signifies your acceptance of the Terms of Use.