Parallel Decoding Cyclic Burst Error Correcting Codes

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http://doi.ieeecomputersociety.org/10.1109/TC.2005.9

January 2005 (vol. 54 no. 1) pp. 87-92

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	Ganesan Umanesan, Eiji Fujiwara, "Parallel Decoding Cyclic Burst Error Correcting Codes," IEEE Transactions on Computers, vol. 54, no. 1, pp. 87-92, January, 2005.

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	@article{ 10.1109/TC.2005.9, author = {Ganesan Umanesan and Eiji Fujiwara}, title = {Parallel Decoding Cyclic Burst Error Correcting Codes}, journal ={IEEE Transactions on Computers}, volume = {54}, number = {1}, issn = {0018-9340}, year = {2005}, pages = {87-92}, doi = {http://doi.ieeecomputersociety.org/10.1109/TC.2005.9}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - JOUR JO - IEEE Transactions on Computers TI - Parallel Decoding Cyclic Burst Error Correcting Codes IS - 1 SN - 0018-9340 SP87 EP92 EPD - 87-92 A1 - Ganesan Umanesan, A1 - Eiji Fujiwara, PY - 2005 KW - Cyclic burst error correcting codes KW - Fire codes KW - parallel decoding KW - companion matrix. VL - 54 JA - IEEE Transactions on Computers ER -

Ganesan Umanesan, IEEE

Eiji Fujiwara, IEEE

Burst error correcting codes, such as Fire codes, have traditionally been decoded using Linear Feedback Shift Registers (LFSR). However, such sequential decoding schemes are not suitable for modern ultra high-speed channels that demand high-speed parallel decoding employing only combinational logic circuitry. This paper proposes a parallel decoding method for cyclic burst error correcting codes. Under this method, a binary companion matrix T defines the entire decoding process. Hence, the decoding method can be implemented using only combinational logic.

[1] 87 T.R.N. Rao and E. Fujiwara, Error Control Coding for Computer Systems. Prentice Hall, 1989.
[2] J.E. Meggitt, “Error Correcting Codes and Their Implementation for Data Transmission Systems,” IRE Trans. Information Theory, vol. 7, pp. 232-244, 1961.
[3] R.T. Chien, “Burst-Correcting Codes with High-Speed Decoding,” IEEE Trans. Information Theory, vol. 15, pp. 109-113, Jan. 1969.
[4] Y. Katayama and S. Morioka, “One-Shot Reed-Solomon Decoding for High-Performance Dependable Systems,” Proc. 2000 Int'l Conf. Dependable Systems and Networks (DSN 2000), June 2000.
[5] E. Fujiwara, K. Namba, and M. Kitakami, “Parallel Decoding for Burst Error Control Codes,” Proc. IEEE 2002 Int'l Symp. Information Theory (ISIT 2002), 2002.
[6] E. Fujiwara, K. Namba, and M. Kitakami, “Parallel Decoding for Burst Error Control Codes,” Electronics and Comm. in Japan, vol. 87, no. 1, pp. 38-48, Jan. 2004.
[7] W. Peterson Jr and E.J. Weldon, Error-Correcting Codes. MIT Press, 1972.

Index Terms:

Cyclic burst error correcting codes, Fire codes, parallel decoding, companion matrix.

Citation:

Ganesan Umanesan, Eiji Fujiwara, "Parallel Decoding Cyclic Burst Error Correcting Codes," IEEE Transactions on Computers, vol. 54, no. 1, pp. 87-92, Jan. 2005, doi:10.1109/TC.2005.9

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