Cache Memory Design for Internet Processors

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http://doi.ieeecomputersociety.org/10.1109/40.820050

January/February 2000 (vol. 20 no. 1) pp. 28-33

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	ASCII Text	x
	Tzi-cker Chiueh, Prashant Pradhan, "Cache Memory Design for Internet Processors," IEEE Micro, vol. 20, no. 1, pp. 28-33, January/February, 2000.

	BibTex	x
	@article{ 10.1109/40.820050, author = {Tzi-cker Chiueh and Prashant Pradhan}, title = {Cache Memory Design for Internet Processors}, journal ={IEEE Micro}, volume = {20}, number = {1}, issn = {0272-1732}, year = {2000}, pages = {28-33}, doi = {http://doi.ieeecomputersociety.org/10.1109/40.820050}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - MGZN JO - IEEE Micro TI - Cache Memory Design for Internet Processors IS - 1 SN - 0272-1732 SP28 EP33 EPD - 28-33 A1 - Tzi-cker Chiueh, A1 - Prashant Pradhan, PY - 2000 VL - 20 JA - IEEE Micro ER -

Tzi-cker Chiueh

Prashant Pradhan

We evaluate a series of three progressively more aggressive routing-table cache designs and demonstrate that the incorporation of hardware caches into Internet processors, combined with efficient caching algorithms can significantly improve overall packet forwarding performance.

Citation:

Tzi-cker Chiueh, Prashant Pradhan, "Cache Memory Design for Internet Processors," IEEE Micro, vol. 20, no. 1, pp. 28-33, Jan./Feb. 2000, doi:10.1109/40.820050

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