loading...
An Optimizer for Hardware Synthesis
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/54.60604September/October 1990 (vol. 7 no. 5) pp. 20-36
 This Article 
 
Buy PURCHASE ARTICLE: $19
PDF
HTML
Buy IEEE Xplore Subscribers
 
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
ASCII Text
x 
 
J. Bhasker, Huan-Chih Lee, "An Optimizer for Hardware Synthesis," IEEE Design and Test of Computers, vol. 7, no. 5, pp. 20-36, September/October, 1990.
 
 
BibTex
x
 
@article{ 10.1109/54.60604,
author = {J. Bhasker and Huan-Chih Lee},
title = {An Optimizer for Hardware Synthesis},
journal ={IEEE Design and Test of Computers},
volume = {7},
number = {5},
issn = {0740-7475},
year = {1990},
pages = {20-36},
doi = {http://doi.ieeecomputersociety.org/10.1109/54.60604},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - MGZN
JO - IEEE Design and Test of Computers
TI - An Optimizer for Hardware Synthesis
IS - 5
SN - 0740-7475
SP20
EP36
EPD - 20-36
A1 - J. Bhasker,
A1 - Huan-Chih Lee,
PY - 1990
VL - 7
JA - IEEE Design and Test of Computers
ER -
 

A description is given of a process-graph analyzer, i.e. a program that optimizes an algorithmic hardware description while endeavoring to attain maximum speed with the minimum commitment to resources. The analyzer is part of the V-Synth system. The four major subsystems of the analyzer-the decomposer, the optimizer, the control-state generator, and the translator-are discussed. Because both its input and output are in VHDL, VHDL itself is discussed. Preliminary test results for the analyzer are presented.

Citation:
J. Bhasker, Huan-Chih Lee, "An Optimizer for Hardware Synthesis," IEEE Design and Test of Computers, vol. 7, no. 5, pp. 20-36, Sep./Oct. 1990, doi:10.1109/54.60604
Usage of this product signifies your acceptance of the Terms of Use.