This article presents a fault model and testing strategies for a 2-bit per cell dynamic random-access memory (DRAM). Multilevel DRAM technology may become an important way of increasing the storage density of semiconductor memory for a given process and minimum feature size. The multilevel DRAM that we consider re-uses many proven elements from a conventional 1-bit per cell DRAM cell array. From a list of reported DRAM physical defects we develop a fault model using both manual analysis and analog simulation. Several alternative testing strategies are proposed that make different trade-offs between testing cost and possible design for testability enhancements.