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Estimating Circuit Activity in Combinational CMOS Digital Circuits
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/54.844340April-June 2000 (vol. 17 no. 2) pp. 112-119
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Hendrawan Soeleman, Kaushik Roy, Tan-Li Chou, "Estimating Circuit Activity in Combinational CMOS Digital Circuits," IEEE Design and Test of Computers, vol. 17, no. 2, pp. 112-119, April-June, 2000.
 
 
BibTex
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@article{ 10.1109/54.844340,
author = {Hendrawan Soeleman and Kaushik Roy and Tan-Li Chou},
title = {Estimating Circuit Activity in Combinational CMOS Digital Circuits},
journal ={IEEE Design and Test of Computers},
volume = {17},
number = {2},
issn = {0740-7475},
year = {2000},
pages = {112-119},
doi = {http://doi.ieeecomputersociety.org/10.1109/54.844340},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
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TY - MGZN
JO - IEEE Design and Test of Computers
TI - Estimating Circuit Activity in Combinational CMOS Digital Circuits
IS - 2
SN - 0740-7475
SP112
EP119
EPD - 112-119
A1 - Hendrawan Soeleman,
A1 - Kaushik Roy,
A1 - Tan-Li Chou,
PY - 2000
VL - 17
JA - IEEE Design and Test of Computers
ER -
 

Fast and accurate probabilistic and statistical techniques for estimating circuit activity in CMOS digital circuits offer an alternative to circuit simulation. The techniques use statistics of input signals to determine accurate switching information.

Citation:
Hendrawan Soeleman, Kaushik Roy, Tan-Li Chou, "Estimating Circuit Activity in Combinational CMOS Digital Circuits," IEEE Design and Test of Computers, vol. 17, no. 2, pp. 112-119, Apr.-June 2000, doi:10.1109/54.844340
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