Rolf Clauberg, Peter Buchmann, Andreas Herkersdorf, David J. Webb,
"Design Methodology for a Large Communication Chip,"
IEEE Design and Test of Computers, vol. 17, no. 3, pp. 86-94, July-September, 2000.
BibTex
x
@article{
10.1109/54.867899, author = {Rolf Clauberg and Peter Buchmann and Andreas Herkersdorf and David J. Webb}, title = {Design Methodology for a Large Communication Chip}, journal ={IEEE Design and Test of Computers}, volume = {17}, number = {3}, issn = {0740-7475}, year = {2000}, pages = {86-94}, doi = {http://doi.ieeecomputersociety.org/10.1109/54.867899}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }
RefWorks Procite/RefMan/Endnote
x
TY - MGZN JO - IEEE Design and Test of Computers TI - Design Methodology for a Large Communication Chip IS - 3 SN - 0740-7475 SP86 EP94 EPD - 86-94 A1 - Rolf Clauberg, A1 - Peter Buchmann, A1 - Andreas Herkersdorf, A1 - David J. Webb, PY - 2000 VL - 17 JA - IEEE Design and Test of Computers ER -
The example chip operates with 14 externally provided system clocks plus four clocks recovered from input data streams and 36 corresponding internal clock domains. It also couples a large digital design to a mixed-signal part in physical design.
Citation:
Rolf Clauberg, Peter Buchmann, Andreas Herkersdorf, David J. Webb, "Design Methodology for a Large Communication Chip," IEEE Design and Test of Computers, vol. 17, no. 3, pp. 86-94, July-Sept. 2000, doi:10.1109/54.867899
PURCHASE ARTICLE: $19
IEEE Xplore Subscribers
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb