Pramodchandran N. Variyam, Abhijit Chatterjee,
"Digital-Compatible BIST for Analog Circuits Using Transient Response Sampling,"
IEEE Design and Test of Computers, vol. 17, no. 3, pp. 106-115, July-September, 2000.
BibTex
x
@article{
10.1109/54.867901, author = {Pramodchandran N. Variyam and Abhijit Chatterjee}, title = {Digital-Compatible BIST for Analog Circuits Using Transient Response Sampling}, journal ={IEEE Design and Test of Computers}, volume = {17}, number = {3}, issn = {0740-7475}, year = {2000}, pages = {106-115}, doi = {http://doi.ieeecomputersociety.org/10.1109/54.867901}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }
RefWorks Procite/RefMan/Endnote
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TY - MGZN JO - IEEE Design and Test of Computers TI - Digital-Compatible BIST for Analog Circuits Using Transient Response Sampling IS - 3 SN - 0740-7475 SP106 EP115 EPD - 106-115 A1 - Pramodchandran N. Variyam, A1 - Abhijit Chatterjee, PY - 2000 VL - 17 JA - IEEE Design and Test of Computers ER -
For complex mixed-signal designs, BIST is becoming a necessity. The BIST scheme presented here maximizes coverage of parametric and catastrophic failures and provides an all-digital BIST solution to analog circuits.
Citation:
Pramodchandran N. Variyam, Abhijit Chatterjee, "Digital-Compatible BIST for Analog Circuits Using Transient Response Sampling," IEEE Design and Test of Computers, vol. 17, no. 3, pp. 106-115, July-Sept. 2000, doi:10.1109/54.867901
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