System-on-Chip Testability Using LSSD Scan Structures

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http://doi.ieeecomputersociety.org/10.1109/54.922805

May/June 2001 (vol. 18 no. 3) pp. 83-97

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	Kamran Zarrineh, Shambhu J. Upadhyaya, Vivek Chickermane, "System-on-Chip Testability Using LSSD Scan Structures," IEEE Design and Test of Computers, vol. 18, no. 3, pp. 83-97, May/June, 2001.

	BibTex	x
	@article{ 10.1109/54.922805, author = {Kamran Zarrineh and Shambhu J. Upadhyaya and Vivek Chickermane}, title = {System-on-Chip Testability Using LSSD Scan Structures}, journal ={IEEE Design and Test of Computers}, volume = {18}, number = {3}, issn = {0740-7475}, year = {2001}, pages = {83-97}, doi = {http://doi.ieeecomputersociety.org/10.1109/54.922805}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - MGZN JO - IEEE Design and Test of Computers TI - System-on-Chip Testability Using LSSD Scan Structures IS - 3 SN - 0740-7475 SP83 EP97 EPD - 83-97 A1 - Kamran Zarrineh, A1 - Shambhu J. Upadhyaya, A1 - Vivek Chickermane, PY - 2001 VL - 18 JA - IEEE Design and Test of Computers ER -

Kamran Zarrineh

Shambhu J. Upadhyaya

Vivek Chickermane

A technology-independent test synthesis tool extends the basic level-sensitive scan design (LSSD) boundary scan methodology. It reuses functional storage elements wherever possible and introduces minimal test logic overhead and delay.

Citation:

Kamran Zarrineh, Shambhu J. Upadhyaya, Vivek Chickermane, "System-on-Chip Testability Using LSSD Scan Structures," IEEE Design and Test of Computers, vol. 18, no. 3, pp. 83-97, May/June 2001, doi:10.1109/54.922805

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