Reinaldo A. Bergamaschi, Subhrajit Bhattacharya, Ronoldo Wagner, Colleen Fellenz, Michael Muhlada, William R. Lee, Foster White, Jean-Marc Daveau,
"Automating the Design of SOCs Using Cores,"
IEEE Design and Test of Computers, vol. 18, no. 5, pp. 32-45, September/October, 2001.
BibTex
x
@article{
10.1109/54.953270, author = {Reinaldo A. Bergamaschi and Subhrajit Bhattacharya and Ronoldo Wagner and Colleen Fellenz and Michael Muhlada and William R. Lee and Foster White and Jean-Marc Daveau}, title = {Automating the Design of SOCs Using Cores}, journal ={IEEE Design and Test of Computers}, volume = {18}, number = {5}, issn = {0740-7475}, year = {2001}, pages = {32-45}, doi = {http://doi.ieeecomputersociety.org/10.1109/54.953270}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }
RefWorks Procite/RefMan/Endnote
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TY - MGZN JO - IEEE Design and Test of Computers TI - Automating the Design of SOCs Using Cores IS - 5 SN - 0740-7475 SP32 EP45 EPD - 32-45 A1 - Reinaldo A. Bergamaschi, A1 - Subhrajit Bhattacharya, A1 - Ronoldo Wagner, A1 - Colleen Fellenz, A1 - Michael Muhlada, A1 - William R. Lee, A1 - Foster White, A1 - Jean-Marc Daveau, PY - 2001 VL - 18 JA - IEEE Design and Test of Computers ER -
Assembling a system on a chip using IP blocks is an error-prone, labor-intensive, and time-consuming process. Emerging high-level tools can help by automating many of the design tasks.
Citation:
Reinaldo A. Bergamaschi, Subhrajit Bhattacharya, Ronoldo Wagner, Colleen Fellenz, Michael Muhlada, William R. Lee, Foster White, Jean-Marc Daveau, "Automating the Design of SOCs Using Cores," IEEE Design and Test of Computers, vol. 18, no. 5, pp. 32-45, Sep./Oct. 2001, doi:10.1109/54.953270
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