Zhanping Chen, Liqiong Wei, Ali Keshavarzi, Kaushik Roy,
"IDDQ Testing for Deep-Submicron ICs: Challenges and Solutions,"
IEEE Design and Test of Computers, vol. 19, no. 2, pp. 24-33, March/April, 2002.
BibTex
x
@article{
10.1109/54.990439, author = {Zhanping Chen and Liqiong Wei and Ali Keshavarzi and Kaushik Roy}, title = {IDDQ Testing for Deep-Submicron ICs: Challenges and Solutions}, journal ={IEEE Design and Test of Computers}, volume = {19}, number = {2}, issn = {0740-7475}, year = {2002}, pages = {24-33}, doi = {http://doi.ieeecomputersociety.org/10.1109/54.990439}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }
RefWorks Procite/RefMan/Endnote
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TY - MGZN JO - IEEE Design and Test of Computers TI - IDDQ Testing for Deep-Submicron ICs: Challenges and Solutions IS - 2 SN - 0740-7475 SP24 EP33 EPD - 24-33 A1 - Zhanping Chen, A1 - Liqiong Wei, A1 - Ali Keshavarzi, A1 - Kaushik Roy, PY - 2002 VL - 19 JA - IEEE Design and Test of Computers ER -
The use of low-threshold devices in scaled low-voltage CMOS circuits leads to increased intrinsic leakage current. As a result, IDDQ testing requires different techniques to remain effective.
Citation:
Zhanping Chen, Liqiong Wei, Ali Keshavarzi, Kaushik Roy, "IDDQ Testing for Deep-Submicron ICs: Challenges and Solutions," IEEE Design and Test of Computers, vol. 19, no. 2, pp. 24-33, Mar./Apr. 2002, doi:10.1109/54.990439
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