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Controllable Delay-Insensitive Processes and their Reflection, Interaction and Factorisation
St. Malo, France June 07-June 09
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ACSD.2005.9Fifth International Conference on App ...
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Hemangee Kapoor, Dhirubhai Ambani Institute of Information and Communication Technology
Mark Josephs, Centre for Concurrent Systems and VLSI
Delay-insensitive processes are typically implemented as asynchronous logic blocks; the possibility of transmission interference along the wires that connect them is considered to be a design error. Using DI-Algebra, the concepts of controllability, reflection, testing by interaction, and design by factorisation are explored. In general, a controllable process should be twice reflected so as to make it as abstract as possible.
Citation:
Hemangee Kapoor, Mark Josephs, "Controllable Delay-Insensitive Processes and their Reflection, Interaction and Factorisation," acsd, pp.58-67, Fifth International Conference on Application of Concurrency to System Design (ACSD'05), 2005
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