In this paper, we present the architecture and implementation of an FPGA-based lookup circuit for a session-based IP packet classifier. The concept of session-based packet classification is summarized and the difference between the traditional- and sessionbased- classification is discussed. A preliminary hardware based architecture customised for FPGA technology is explored and its implementation using Altera Cyclone II technology is outlined. A detailed circuit analysis is presented.
Citation:
Motasem Abdelghani, Sakir Sezer, Emi Garcia, Jun Mu, Ciaran Toal, "FPGA-Based Lookup Circuit for Session-Based IP Packet Classification," ahs, pp.619-624, Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007), 2007