A Low Power Implementation of H.264 Adaptive Deblocking Filter Algorithm

University of Edinburgh, Scotland, United Kingdom August 05-August 08

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http://doi.ieeecomputersociety.org/10.1109/AHS.2007.7

Second NASA/ESA Conference on Adaptiv ...

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	Mustafa Parlak, Ilker Hamzaoglu, "A Low Power Implementation of H.264 Adaptive Deblocking Filter Algorithm," Adaptive Hardware and Systems, NASA/ESA Conference on, pp. 127-133, Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007), 2007.

	BibTex	x
	@article{ 10.1109/AHS.2007.7, author = {Mustafa Parlak and Ilker Hamzaoglu}, title = {A Low Power Implementation of H.264 Adaptive Deblocking Filter Algorithm}, journal ={Adaptive Hardware and Systems, NASA/ESA Conference on}, volume = {0}, year = {2007}, isbn = {0-7695-2866-X}, pages = {127-133}, doi = {http://doi.ieeecomputersociety.org/10.1109/AHS.2007.7}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Adaptive Hardware and Systems, NASA/ESA Conference on TI - A Low Power Implementation of H.264 Adaptive Deblocking Filter Algorithm SN - 0-7695-2866-X SP127 EP133 A1 - Mustafa Parlak, A1 - Ilker Hamzaoglu, PY - 2007 KW - null VL - 0 JA - Adaptive Hardware and Systems, NASA/ESA Conference on ER -

Mustafa Parlak, Sabanci University, Tuzla, 34956, Istanbul, Turkey

Ilker Hamzaoglu, Sabanci University, Tuzla, 34956, Istanbul, Turkey

In this paper, we present a low power implementation of H.264 adaptive deblocking filter (DBF) algorithm on ARM Versatile / PB926EJ-S Development Board. The DBF hardware is implemented using Verilog HDL. An AHB bus interface is designed and integrated into DBF hardware in order to communicate with ARM processor and SRAM through AHB bus. An efficient memory hierarchy and data transfer scheme is also implemented. The DBF hardware implementation works at 72 MHz in a Xilinx Virtex II FPGA and it can code 30 CIF frames (352x288) per second. The power consumption of DBF hardware is analyzed and up to 13% power savings is achieved by applying clock gating and glitch reduction techniques to DBF datapath.

Citation:

Mustafa Parlak, Ilker Hamzaoglu, "A Low Power Implementation of H.264 Adaptive Deblocking Filter Algorithm," ahs, pp.127-133, Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007), 2007

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