The Design and Implementation of a Shared Packet Buffer Architecture for Fixed and Variable Sized Packets

Lisbon, Portugal July 17-July 22

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http://doi.ieeecomputersociety.org/10.1109/AICT.2005.88

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	Stephen O?Kane, Colm McKillen, Sakir Sezer, "The Design and Implementation of a Shared Packet Buffer Architecture for Fixed and Variable Sized Packets," Advanced Industrial Conference on Telecommunications/Service Assurance with Partial and Intermittent Resources Conference/E-Learning on Telecommunications Workshop, pp. 352-356, Advanced Industrial Conference on Telecommunications/Service Assurance with Partial and Intermittent Resources Conference/E-Learning on Telecommunications Workshop (AICT/SAPIR/ELETE'05), 2005.

	BibTex	x
	@article{ 10.1109/AICT.2005.88, author = {Stephen O?Kane and Colm McKillen and Sakir Sezer}, title = {The Design and Implementation of a Shared Packet Buffer Architecture for Fixed and Variable Sized Packets}, journal ={Advanced Industrial Conference on Telecommunications/Service Assurance with Partial and Intermittent Resources Conference/E-Learning on Telecommunications Workshop}, volume = {0}, year = {2005}, isbn = {0-7695-2388-9}, pages = {352-356}, doi = {http://doi.ieeecomputersociety.org/10.1109/AICT.2005.88}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Advanced Industrial Conference on Telecommunications/Service Assurance with Partial and Intermittent Resources Conference/E-Learning on Telecommunications Workshop TI - The Design and Implementation of a Shared Packet Buffer Architecture for Fixed and Variable Sized Packets SN - 0-7695-2388-9 SP352 EP356 A1 - Stephen O?Kane, A1 - Colm McKillen, A1 - Sakir Sezer, PY - 2005 KW - reg VL - 0 JA - Advanced Industrial Conference on Telecommunications/Service Assurance with Partial and Intermittent Resources Conference/E-Learning on Telecommunications Workshop ER -

Stephen O?Kane, Queens University Belfast

Colm McKillen, Queens University Belfast

Sakir Sezer, Queens University Belfast

In this paper, we explore the issues of designing a shared buffer architecture for buffering fixed and variable sized packets. The design and implementation of a shared buffer circuit based on Altera Stratix 2 FPGA technology is presented. The proposed architecture is economic from the resource sharing point of view and is capable supporting buffer bandwidths in excess of 6 Gbps using standard FPGA technology.

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Stephen O?Kane, Colm McKillen, Sakir Sezer, "The Design and Implementation of a Shared Packet Buffer Architecture for Fixed and Variable Sized Packets," aict-sapir-elete, pp.352-356, Advanced Industrial Conference on Telecommunications/Service Assurance with Partial and Intermittent Resources Conference/E-Learning on Telecommunications Workshop (AICT/SAPIR/ELETE'05), 2005

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