A New Architecture For Branch-Intensive Loops

Shanghai, CHINA March 19-March 21

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http://doi.ieeecomputersociety.org/10.1109/APDC.1997.574039

1997 Advances in Parallel and Distrib ...

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	ASCII Text	x
	Zhizhong Tang, Chihong Zhang, Sifei Lvand Tao Yu, "A New Architecture For Branch-Intensive Loops," Advances in Parallel and Distributed Computing Conference, pp. 241, 1997 Advances in Parallel and Distributed Computing Conference (APDC '97), 1997.

	BibTex	x
	@article{ 10.1109/APDC.1997.574039, author = {Zhizhong Tang and Chihong Zhang and Sifei Lvand Tao Yu}, title = {A New Architecture For Branch-Intensive Loops}, journal ={Advances in Parallel and Distributed Computing Conference}, volume = {0}, year = {1997}, isbn = {0-8186-7876-3}, pages = {241}, doi = {http://doi.ieeecomputersociety.org/10.1109/APDC.1997.574039}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Advances in Parallel and Distributed Computing Conference TI - A New Architecture For Branch-Intensive Loops SN - 0-8186-7876-3 SP EP A1 - Zhizhong Tang, A1 - Chihong Zhang, A1 - Sifei Lvand Tao Yu, PY - 1997 KW - software pipelining KW - optimizing schedule KW - branch processing. VL - 0 JA - Advances in Parallel and Distributed Computing Conference ER -

Zhizhong Tang, Tsinghua University

Chihong Zhang, Tsinghua University

Sifei Lvand Tao Yu, Tsinghua University

A new VLIW architecture, called GPMB(Global Pipelining of Multi-Branch), is discussed in this paper. The GPMB architecture can handle branch-intensive programs efficiently. With the concept of next address Function, GPMB regards branching as correctly calculating the next address. The next address function is implemented by hardware and software in GPMB. A brief description of GPMB and a detailed example are included. A comparison with other architectures is also presented in this paper.

Index Terms:

software pipelining, optimizing schedule, branch processing.

Citation:

Zhizhong Tang, Chihong Zhang, Sifei Lvand Tao Yu, "A New Architecture For Branch-Intensive Loops," apdc, pp.241, 1997 Advances in Parallel and Distributed Computing Conference (APDC '97), 1997

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