This paper presents the detailed design of the ARM VFP11 Divide and Square Root synthesisable macrocell. The macrocell was designed using the minimum-redundancy radix-4 SRT digit recurrence algorithm, and this paper describes a novel acceleration technique employed to achieve the required processor clock frequency of up to 750MHz in 90nm CMOS. Logical Effort theory is used to provide a delay analysis of the unit, which demonstrates the balanced nature of the two critical paths therein.