The successful design of high-speed parallel adders depend mainly on fast calculation of carry signals. A technique based on combining Manchester-Carry chains (MCC) with Clock-and-Data pre-charged dynamic logic blocks (CDPD) is suggested and analysed. This technique, as well as pure MCC and CDPD techniques, was incorporated into the design of carry calculation trees. Simulations indicate that 11-25% decrease of delay at the same time as a 19-29% reduction of power consumption is made possible by combining MCCs with CDPD gates instead of using trees consisting solely of either MCCs of CDPD gates.
Index Terms:
CMOS logic circuits; adders; parallel processing; digital arithmetic; VLSI; carry logic; logic design; delays; dynamic CMOS circuit techniques; delay reduction; power reduction; parallel adders; high-speed adders; Manchester-carry chains; clock/data precharged dynamic logic blocks; carry calculation trees; power consumption
Citation:
H. Lindkvist, P. Andersson, "Dynamic CMOS circuit techniques for delay and power reduction in parallel adders," arvlsi, pp.121, 16th Conference on Advanced Research in VLSI (ARVLSI'95), 1995
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