H. Dhanesha, Center for Integrated Syst., Stanford Univ., CA, US
K. Falakshahi, Center for Integrated Syst., Stanford Univ., CA, US
M. Horowitz, Center for Integrated Syst., Stanford Univ., CA, US
A Abstract: This paper presents a new architecture style for the design of a parallel floating point multiplier. The proposed architecture is a synergy of trees and arrays. Architectural models were designed to implement the 53-bit mantissa path of the IEEE standard 754 for floating point multiplication, and tested for functionality in Verilog. The design, which was done in dual-rail domino, simulated in HSpice with estimated capacitive load models in a 1 /spl mu/m CMOS technology. Multiplication latency of 10 ns (23.3 FO4) at 4.3 V supply and 120/spl deg/C can be achieved with the best topology of the array-of-arrays architecture. The estimated multiplier area is 3 mm/spl times/6 mm.
Index Terms:
parallel architectures; floating point arithmetic; multiplying circuits; array-of-arrays architecture; parallel floating point multiplication; synergy; trees; mantissa path; IEEE standard 754; Verilog; dual-rail domino; HSpice simulation; capacitive load model; CMOS technology; latency; 53 bit; 1 micron; 10 ns; 4.3 V; 120 C
Citation:
H. Dhanesha, K. Falakshahi, M. Horowitz, "Array-of-arrays architecture for parallel floating point multiplication," arvlsi, pp.150, 16th Conference on Advanced Research in VLSI (ARVLSI'95), 1995
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