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Code density optimization for embedded DSP processors using data compression techniques
Chapel Hill, North Carolina March 27-March 29
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ARVLSI.1995.51562616th Conference on Advanced Research ...
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S.Y. Liao, Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA
S. Devadas, Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA
K. Keutzer, Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA
We address the problem of code size minimization in VLSI systems with embedded DSP processors. Reducing code size reduces the production cost of embedded systems. We use data compression methods to develop code size minimization strategies. We present a framework for code size minimization where the compressed data consists of a dictionary and a skeleton. The dictionary can be computed using popular text compression algorithms. We describe two methods to execute the compressed code that have varying performance characteristics and varying degrees of freedom in compressing the code. Experimental results obtained with a TMS320C25 code generator are presented.
Index Terms:
minimisation; digital signal processing chips; data compression; VLSI; code density optimization; embedded DSP processors; data compression; code size minimization; VLSI systems; production cost; dictionary; text compression algorithms; TMS320C25 code generator; skeleton
Citation:
S.Y. Liao, S. Devadas, K. Keutzer, "Code density optimization for embedded DSP processors using data compression techniques," arvlsi, pp.272, 16th Conference on Advanced Research in VLSI (ARVLSI'95), 1995
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