Interconnect-Dominated VLSI Design

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http://doi.ieeecomputersociety.org/10.1109/ARVLSI.1999.756042

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	ASCII Text	x
	P. Ghosh, R. Mangaser, C. Mark, K. Rose, "Interconnect-Dominated VLSI Design," Advanced Research in VLSI, Conference on, pp. 114, 20th Anniversary Conference on Advanced Research in VLSI, 1999.

	BibTex	x
	@article{ 10.1109/ARVLSI.1999.756042, author = {P. Ghosh and R. Mangaser and C. Mark and K. Rose}, title = {Interconnect-Dominated VLSI Design}, journal ={Advanced Research in VLSI, Conference on}, volume = {0}, year = {1999}, issn = {1522-869X}, pages = {114}, doi = {http://doi.ieeecomputersociety.org/10.1109/ARVLSI.1999.756042}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Advanced Research in VLSI, Conference on TI - Interconnect-Dominated VLSI Design SN - 1522-869X SP EP A1 - P. Ghosh, A1 - R. Mangaser, A1 - C. Mark, A1 - K. Rose, PY - 1999 KW - Interconnects KW - Microprocessor Performance Estimation KW - Repeater Insertion KW - Floorplanning KW - VLSI Design VL - 0 JA - Advanced Research in VLSI, Conference on ER -

P. Ghosh, Rensselaer Polytechnic Institute

R. Mangaser, Rensselaer Polytechnic Institute

C. Mark, Rensselaer Polytechnic Institute

K. Rose, Rensselaer Polytechnic Institute

This paper demonstrates the problems long, lossy wires pose for VLSI design as devices shrink to deep submicron dimensions. The degree to which both repeater insertion and reverse scaling of wire sizes are required to meet GHz clock frequency projections are estimated using a detailed wire distribution and a detailed processor model (RIPE). We also show how to achieve good floorplans with repeater insertion.

Index Terms:

Interconnects, Microprocessor Performance Estimation, Repeater Insertion, Floorplanning, VLSI Design

Citation:

P. Ghosh, R. Mangaser, C. Mark, K. Rose, "Interconnect-Dominated VLSI Design," arvlsi, pp.114, 20th Anniversary Conference on Advanced Research in VLSI, 1999

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